research-article

Memory efficient software synthesis with mixed coding style from dataflow graphs

Authors:

Wonyong Sung,

Soonhoi HaAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 8, Issue 5

Pages 522 - 526

https://doi.org/10.1109/92.894156

Published: 01 October 2000 Publication History

Abstract

This paper presents a set of techniques to reduce the code and data sizes for software synthesis from graphical digital signal-processing programs based on the synchronous dataflow model. By sharing the kernel code among multiple instances of a block with a shared function, we can further reduce the code size below the previous results based on inline coding style. A systematic approach also is devised to give up the single appearance schedule for reducing the data buffer requirement. The proposed techniques have been evaluated with two real-life examples to prove their significance.

Cited By

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Ma MSakellariou R(2021)Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore SystemsACM Transactions on Embedded Computing Systems10.1145/344003420:3(1-24)Online publication date: 27-Mar-2021
https://dl.acm.org/doi/10.1145/3440034
Lee DOh H(2013)A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memoryACM Transactions on Embedded Computing Systems10.1145/2435227.243523212:1s(1-17)Online publication date: 21-Mar-2013
https://dl.acm.org/doi/10.1145/2435227.2435232
Wang AHahn JRoumi MChou P(2012)Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral TransparencyACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234884517:4(1-26)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348845
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Index Terms

Memory efficient software synthesis with mixed coding style from dataflow graphs
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Datapath optimization
    2. Logic synthesis
      1. Circuit optimization
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 8, Issue 5

Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)

Oct., 2000

174 pages

ISSN:1063-8210

Editors:
Wayne Wolf
Princeton Univ., Princeton, NJ
,
Allen C.-H. Wu
Tsing Hua Univ., Hsinchu, Taiwan
,
Nikil D. Dutt
Univ. of California, Irvine, Irvine

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IEEE Educational Activities Department

United States

Publication History

Published: 01 October 2000

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Cited By

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Ma MSakellariou R(2021)Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore SystemsACM Transactions on Embedded Computing Systems10.1145/344003420:3(1-24)Online publication date: 27-Mar-2021
https://dl.acm.org/doi/10.1145/3440034
Lee DOh H(2013)A lifetime aware buffer assignment method for streaming applications on DRAM/PRAM hybrid memoryACM Transactions on Embedded Computing Systems10.1145/2435227.243523212:1s(1-17)Online publication date: 21-Mar-2013
https://dl.acm.org/doi/10.1145/2435227.2435232
Wang AHahn JRoumi MChou P(2012)Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral TransparencyACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234884517:4(1-26)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348845
Jung HYang HHa S(2008)Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW CosynthesisJournal of Signal Processing Systems10.1007/s11265-007-0070-952:1(13-34)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1007/s11265-007-0070-9
Hahn JChou PKirsch CWilhelm R(2007)Buffer optimization and dispatching scheme for embedded systems with behavioral transparencyProceedings of the 7th ACM & IEEE international conference on Embedded software10.1145/1289927.1289946(94-103)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289927.1289946
Ko MMurthy PBhattacharyya S(2007)Beyond single-appearance schedulesACM Transactions on Embedded Computing Systems10.1145/1234675.12346816:2(14-es)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1145/1234675.1234681
Oh HDutt NHa SHirose F(2006)Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118420(497-502)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118420
Oh HDutt NHa SConte TFaraboschi PMangione-Smith BNajjar W(2005)Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphsProceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1086297.1086318(157-165)Online publication date: 24-Sep-2005
https://dl.acm.org/doi/10.1145/1086297.1086318
Oh HHa S(2004)Fractional Rate Dataflow Model for Efficient Code SynthesisJournal of VLSI Signal Processing Systems10.5555/971216.281349137:1(41-51)Online publication date: 1-May-2004
https://dl.acm.org/doi/10.5555/971216.2813491
Oh HHa S(2002)Fractional rate dataflow model and efficient code synthesis for multimedia applicationsACM SIGPLAN Notices10.1145/566225.51383437:7(12-17)Online publication date: 19-Jun-2002
https://dl.acm.org/doi/10.1145/566225.513834
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Efficient code synthesis from extended dataflow graphs for multimedia applications

Software synthesis from the dataflow interchange format

Memory-optimized software synthesis from dataflow program graphs with large size data samples

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