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Data Memory Organization and Optimizations in Application-Specific Systems

Authors:

Preeti Ranjan Panda,

Alexandru Nicolau,

Francky Catthoor,

Arnout Vandecappelle,

Erik Brockmeyer,

Chidamber Kulkarni,

Eddy De GreefAuthors Info & Claims

IEEE Design & Test, Volume 18, Issue 3

Pages 56 - 68

https://doi.org/10.1109/54.922803

Published: 01 May 2001 Publication History

Abstract

In application-specific designs, customized memory organization expands the search space for cost-optimized solutions. Several optimization strategies can be applied to embedded systems with several different memory architectures: data cache, scratch-pad memory, custom memory architectures, and dynamic random-access memory (DRAM).

References

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Digital Library

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P.R. Panda N.D. Dutt and A. Nicolau, Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration, Kluwer Academic Publishers, Norwell, Mass., 1999.

Digital Library

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C. Kulkarni F. Catthoor and H. De Man, "Cache Optimization for Multimedia Compilation on Embedded Processors for Low Power," ACM/IEEE Proc. Parallel Processing Symp. (IPPS), IEEE CS Press, Los Alamitos, Calif., 1998, pp. 292-297.

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C. Kulkarni, et al., "Cache-Conscious Data Layout Organization for Embedded Multimedia Applications," Proc. 4th ACM/IEEE Design and Test in Europe Conf., ACM Press, New York, Mar. 2001.

Digital Library

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P.R. Panda N.D. Dutt and A. Nicolau, "On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-Based Systems," ACM Trans. Design Automation of Electronic Systems, vol. 5, no. 3, July 2000, pp. 682-704.

Digital Library

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P.R. Panda N.D. Dutt and A. Nicolau, "Local Memory Exploration and Optimization in Embedded Systems," IEEE Trans. Computer-Aided Design, vol. 18, no. 1, Jan. 1999, pp. 3-13.

Digital Library

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W.-T. Shiue and C. Chakrabarti, "Memory Exploration for Low Power Embedded Systems," Proc. Design Automation Conf., ACM Press, New York, 1999, pp. 140-145.

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Digital Library

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P-G. Kjeldsberg F. Catthoor and E.J. Aas, "Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE CS Press, Los Alamitos, Calif, 2000, pp. 44-50.

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P.R. Panda, "Memory Bank Customization and Assignment in Behavioral Synthesis," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE CS Press, Los Alamitos, Calif, 1999.

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[16]

P.R. Panda N.D. Dutt and A. Nicolau, "On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-Based Systems," ACM Trans. Design Automation of Electronic Systems, vol. 5, no. 3, July 2000, pp. 682-704.

Digital Library

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P.R. Panda N.D. Dutt and A. Nicolau, Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration, Kluwer Academic Publishers, Norwell, Mass., 1999.

Digital Library

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P. Grun N.D. Dutt and A. Nicolau, "Memory-Aware Compilation through Accurate Timing Extraction," Proc. Design Automation Conf., ACM Press, New York, 2000, pp. 316-321.

Digital Library

Cited By

Bouziane RRohou EGamatié AChillet D(2018)Compile-Time Silent-Store Elimination for Energy EfficiencyProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180666(1-8)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180666
Pilato CMantovani PDi Guglielmo GCarloni L(2017)System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261150636:3(435-448)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2611506
Filippopoulos ISharma NCatthoor FKjeldsberg PPanda P(2016)Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD ArchitecturesACM Transactions on Embedded Computing Systems10.1145/289475415:3(1-23)Online publication date: 23-May-2016
https://dl.acm.org/doi/10.1145/2894754
Show More Cited By

Data Memory Organization and Optimizations in Application-Specific Systems
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information

Published In

cover image IEEE Design & Test

IEEE Design & Test Volume 18, Issue 3

May 2001

123 pages

ISSN:0740-7475

Issue’s Table of Contents

Copyright © Copyright © 2001 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 2001

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Cited By

Bouziane RRohou EGamatié AChillet D(2018)Compile-Time Silent-Store Elimination for Energy EfficiencyProceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3180665.3180666(1-8)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.1145/3180665.3180666
Pilato CMantovani PDi Guglielmo GCarloni L(2017)System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261150636:3(435-448)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2611506
Filippopoulos ISharma NCatthoor FKjeldsberg PPanda P(2016)Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD ArchitecturesACM Transactions on Embedded Computing Systems10.1145/289475415:3(1-23)Online publication date: 23-May-2016
https://dl.acm.org/doi/10.1145/2894754
Wingbermuehle JCytron RChamberlain RConstantinides GChen D(2015)Superoptimized Memory Subsystems for Streaming ApplicationsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689069(126-135)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689069
Wingbermuehle JCytron RChamberlain R(2014)Superoptimization of memory subsystemsACM SIGPLAN Notices10.1145/2666357.259781649:5(145-154)Online publication date: 12-Jun-2014
https://dl.acm.org/doi/10.1145/2666357.2597816
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2656075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656075.2656098
Wingbermuehle JCytron RChamberlain RZhang YKulkarni P(2014)Superoptimization of memory subsystemsProceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2597809.2597816(145-154)Online publication date: 12-Jun-2014
https://dl.acm.org/doi/10.1145/2597809.2597816
Pilato CMantovani PDi Guglielmo GCarloni LMarculescu RNicolescu G(2014)System-level memory optimization for high-level synthesis of component-based SoCsProceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis10.1145/2565075.2656098(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2565075.2656098
(2013)Compiler-directed memory hierarchy design for low-energy embedded systemsProceedings of the Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign10.5555/3041405.3041497(147-156)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.5555/3041405.3041497
Elizeh KNicolici NSapatnekar S(2010)Embedded memory binding in FPGAsProceedings of the 47th Design Automation Conference10.1145/1837274.1837389(457-462)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837389
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