research-article

Gate-level power estimation using tagged probabilistic simulation

Authors:

Chih-Shun Ding,

Chi-Ying Tsui,

M. PedramAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 17, Issue 11

Pages 1099 - 1107

https://doi.org/10.1109/43.736184

Published: 01 November 2006 Publication History

Abstract

In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-3× improvement in accuracy of power estimates over previous probabilistic simulation approaches

Cited By

View all

Zou SZhang JShi BLuo G(2024)PowerSyn: A Logic Synthesis Framework With Early Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.329706943:1(203-216)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3297069
Durrani YRiesgo T(2016)Efficient power analysis approach and its application to system-on-chip designMicroprocessors & Microsystems10.1016/j.micpro.2016.09.00346:PA(11-20)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.09.003
Durrani YRiesgo T(2014)Power estimation for intellectual property-based digital systems at the architectural levelJournal of King Saud University - Computer and Information Sciences10.1016/j.jksuci.2014.03.00526:3(287-295)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1016/j.jksuci.2014.03.005
Show More Cited By

Recommendations

Probabilistic gate-level power estimation using a novel waveform set method
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each circuit node is estimated. Existing methods have local glitch filtering ...
Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic
CSE '14: Proceedings of the 2014 IEEE 17th International Conference on Computational Science and Engineering

Multiplier is the most commonly used circuit in digital devices. Multiplication is one of the basic functions used in digital signal processing. Gate Diffusion Input (GDI) logic reduces the power dissipation and area of digital circuits while ...
The J-K Gate

For many years two-input NAND, AND, NOR, OR and EX-OR gates have been commercially available as cheap quad TTL integrated circuits (IC's). Ideas on quad programmable two-input gates (three inputs per gate) have been published in the literature but have ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 17, Issue 11

November 2006

154 pages

ISSN:0278-0070

Issue’s Table of Contents

Publisher

IEEE Press

Publication History

Published: 01 November 2006

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

21
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 19 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Zou SZhang JShi BLuo G(2024)PowerSyn: A Logic Synthesis Framework With Early Power OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.329706943:1(203-216)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3297069
Durrani YRiesgo T(2016)Efficient power analysis approach and its application to system-on-chip designMicroprocessors & Microsystems10.1016/j.micpro.2016.09.00346:PA(11-20)Online publication date: 1-Oct-2016
https://dl.acm.org/doi/10.1016/j.micpro.2016.09.003
Durrani YRiesgo T(2014)Power estimation for intellectual property-based digital systems at the architectural levelJournal of King Saud University - Computer and Information Sciences10.1016/j.jksuci.2014.03.00526:3(287-295)Online publication date: 1-Sep-2014
https://dl.acm.org/doi/10.1016/j.jksuci.2014.03.005
Wang LOlbrich MBarke EBüchner TBühler MPanitz PPhillips JHu AGraeb H(2011)A theoretical probabilistic simulation framework for dynamic power estimationProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132481(708-715)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132481
Dinh QChen DWong MLin Y(2010)Dynamic power estimation for deep submicron circuits with process variationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899860(587-592)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899860
Czajkowski TBrown S(2010)Decomposition-based vectorless toggle rate computation for FPGA circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206125029:11(1723-1735)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061250
Khalil DSinha DZhou HIsmail Y(2009)A timing-dependent power estimation framework considering couplingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200873917:6(843-847)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2008739
Roy SChakrabarti PDasgupta P(2008)Satisfiability models for maximum transition powerIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200032216:8(941-951)Online publication date: 1-Aug-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000322
Oskuii SKjeldsberg PAas EZhou HMacii EYan ZMassoud Y(2007)Probabilistic gate-level power estimation using a novel waveform set methodProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228799(37-42)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228799
Hu FAgrawal VLach JQu GIsmail Y(2005)Dual-transition glitch filtering in probabilistic waveform power estimationProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057747(357-360)Online publication date: 17-Apr-2005
https://dl.acm.org/doi/10.1145/1057661.1057747
Show More Cited By

Abstract

Cited By

Recommendations

Probabilistic gate-level power estimation using a novel waveform set method

Implementation of Low Power 8-Bit Multiplier Using Gate Diffusion Input Logic

The J-K Gate

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations