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research-article

Communication styles for parallel systems

Published: 01 December 1994 Publication History

Abstract

Distributed-memory parallel systems rely on explicit message exchange for communication, but the communication operations they support can differ in many aspects. One key difference is the way messages are generated or consumed. With systolic communication, a message is transmitted as it is generated. For example, the result computed by the multiplier is sent directly to the communication subsystem for transmission to another node. With memory communication, the complete message is generated and stored in memory, and then transmitted to its destination. Since sender and receiver nodes are individually controlled, they can use different communication styles. One example of memory communication is message passing: both the sender and receiver buffer the message in memory. These two communication styles place different demands on processor design. This article illustrates each style's effect on processor resources for some key application kernels. We are targeting the iWarp system because it supports both communication styles. Two parallel-program generators, one for each communication style, automatically map the sample programs.

References

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1. E. Anderson and J. Dongarra, "Implementation Guide for LAPACK," LAPACK Working Note, No. 18, Tech. Report CS-90-101, Univ. of Tennessee, Knoxville, Tenn., Apr. 1990.
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1. S. Borkar et al., "Supporting Systolic and Memory Communication in iWarp," Proc. 17th Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., Order No. 2047, May 1990, pp. 70-81.
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2. S. Borkar et al., "iWarp: An Integrated Solution to High-Speed Parallel Computing," Proc. Supercomputing 88, Vol. 1, IEEE CS Press, Los Alamitos, Calif., Order No. 882, Nov. 1988, pp. 330-339.
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3. H.B. Ribas, "Automatic Generation of Systolic Programs from Nested Loops," doctoral dissertation, Carnegie Mellon Univ., Pittsburgh, June 1990.
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6. J. Stichnoth, D. O'Hallaron, and T. Gross, "Generating Communication for Array Statements: Design, Implementation, and Evaluation," IEEE Parallel and Distributed Computing, Vol. 21, No. 1, Apr. 1994, pp. 150-159.

Cited By

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  • (2010)A pattern for efficient parallel computation on multicore processors with scalar operand networksProceedings of the 2010 Workshop on Parallel Programming Patterns10.1145/1953611.1953614(1-9)Online publication date: 30-Mar-2010
  • (2005)Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor NetworksProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 0110.1109/IPDPS.2005.416Online publication date: 4-Apr-2005
  1. Communication styles for parallel systems

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    cover image Computer
    Computer  Volume 27, Issue 12
    December 1994
    86 pages

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    IEEE Computer Society Press

    Washington, DC, United States

    Publication History

    Published: 01 December 1994

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    • (2010)A pattern for efficient parallel computation on multicore processors with scalar operand networksProceedings of the 2010 Workshop on Parallel Programming Patterns10.1145/1953611.1953614(1-9)Online publication date: 30-Mar-2010
    • (2005)Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor NetworksProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Papers - Volume 0110.1109/IPDPS.2005.416Online publication date: 4-Apr-2005

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