More Web Proxy on the site http://driver.im/

research-article

Methodologies for Tolerating Cell and Interconnect Faults in FPGAs

Authors:

Shantanu DuttAuthors Info & Claims

IEEE Transactions on Computers, Volume 47, Issue 1

Pages 15 - 33

https://doi.org/10.1109/12.656073

Published: 01 January 1998 Publication History

Abstract

The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational faults. Thus, there is a critical need for fault tolerance and reconfiguration techniques for FPGAs to increase chip yields (with factory reconfiguration) and/or system reliability (with field reconfiguration). We first propose techniques utilizing the principle of node-covering to tolerate logic or cell faults in SRAM-based FPGAs. A routing discipline is developed that allows each cell to cover-to be able to replace-its neighbor in a row. Techniques are also proposed for tolerating wiring faults by means of replacement with spare portions. The replaceable portions can be individual segments, or else sets of segments, called “grids”. Fault detection in the FPGAs is accomplished by separate testing, either at the factory or by the user. If reconfiguration around faulty cells and wiring is performed at the factory (with laser-burned fuses, for example), it is completely transparent to the user. In other words, user configuration data loaded into the SRAM remains the same, independent of whether the chip is detect-free or whether it has been reconfigured around defective cells or wiring-a major advantage for hardware vendors who design and sell FPGA-based logic (e.g., glue logic in microcontrollers, video cards, DSP cards) in production-scale quantities. Compared to other techniques for fault tolerance in FPGAs, our methods are shown to provide significantly greater yield improvement, and a 35 percent non-FT chip yield for a 16×16 FPGA is more than doubled

References

[1]

Altera Corporation, FLEX8000 Programmable Logic Device Family Data Sheet. 1994.]]

[2]

S. Brown, Univ. of Toronto, private communication, May 1995.]]

[3]

R. Cliff, et al., "A Dual Granularity and Globally Interconnected Architecture for a Programmable Logic Device," Proc. IEEE Custom Integrated Circuits Conf., pp. 7.3.1-7.3.5, 1993.]]

[4]

P. Chow, et al., "A 1.2mm CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing," Proc. Oxford 1991 Int'l Workshop Field Programming Logic and Applications, pp. 91-102, FPGAs, W. Moore and W. Luk, eds. Abingdon, England: Abingdon EE & CS Books, 1991.]]

[5]

J. Cunningham, "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," IEEE Trans. Semiconductor Manufacturing, vol. 3, no. 2, pp. 60-71, May 1990.]]

[6]

S. Dutt and F. Hanchek, "REMOD: A New Hardware- and Time-Efficient Methodology for Designing Fault-Tolerant Arithmetic Circuits," IEEE Trans. VLSI Systems, vol. 5, pp. 34-56, Mar. 1997.]]

Digital Library

[7]

S. Dutt and J.P. Hayes, "Some Practical Issues in the Design of Fault-Tolerant Multiprocessors," IEEE Trans. Computers, vol. 41, no. 5, pp. 588-598, May 1992.]]

Digital Library

[8]

S. Dutt and N.R. Mahapatra, "Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance," IEEE Trans. Computers, vol. 46, no. 9, pp. 997-1,015, Sept. 1997.]]

Digital Library

[9]

F. Hanchek and S. Dutt, "Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs," Proc. Int'l Conf. VLSI Design, pp. 225-229, Jan. 1996.]]

Digital Library

[10]

F. Hanchek and S. Dutt, "Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs," Proc. Int'l Conf. Computer Design, pp. 326-331, Oct. 1996.]]

Digital Library

[11]

F. Hanchek and S. Dutt, "Design Methodologies for Tolerating Logic and Interconnect Faults in FPGAs," technical teport, Sept. 1997, http://www.eecs.uic.edu/dutt/tech-reps/ftfpga-tc-ext.ps.]]

[12]

N. Hastie and R. Cliff, "The Implementation of Hardware Subroutines on Field Programmable Gate Arrays," Proc. IEEE Custom Integrated Circuits Conf., pp. 31.4.1-31.4.4, 1990.]]

[13]

F. Hatori, et al., "Introducing Redundancy in Field Programmable Gate Arrays," Proc. IEEE Custom Integrated Circuits Conf., pp. 7.1.1-7.1.4, 1993.]]

[14]

N. Howard A. Tyrrell and N. Allinson, "The Yield Enhancement of Field-Programmable Gate Arrays," IEEE Trans. VLSI Systems, vol. 2, no. 1, pp. 115-123, Mar. 1994.]]

Digital Library

[15]

W.K. Huang X.T. Chen and F. Lombardi, "On the Diagnosis of Programmable Interconnect Systems: Theory and Applications," Proc. 14th IEEE VLSI Test Symp., 1996.]]

Digital Library

[16]

W.K. Huang and F. Lombardi, "An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays," Proc. 14th IEEE VLSI Test Symp., 1996.]]

Digital Library

[17]

M. Khellah S. Brown and Z. Vranesic, "Modelling Routing Delays in SRAM-based FPGAs," Proc. 1993 CCVLSI, pp. 6B.13-6B.18, Nov. 1993.]]

[18]

V. Kumar A. Dahbura F. Fisher and P. Juola, "An Approach for the Yield Enhancement of Programmable Gate Arrays," Proc. IEEE Int'l Conf. Computer-Aided Design, pp. 226-229, Nov. 1989.]]

[19]

J. McDonald B. Philhower and H. Greub, "A Fine Grained, Highly Fault-tolerant System Based on WSI and FPGA Technology," Proc. Oxford 1991 Int'l Workshop Field Programming Logic Applications, pp. 114-126, FPGAs, W. Moore and W. Luk, eds. Abingdon, England: Abingdon EE & CS Books, 1991.]]

[20]

J. Narasimhan K. Nakajima C. Rim and A. Dahbura, "Yield Enhancement of Programmable ASIC Arrays by Reconfiguration of Circuit Placements," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 8, pp. 976-986, Aug. 1994.]]

Digital Library

[21]

K. Roy and S. Nag, "On Routability for FPGAs under Faulty Conditions," IEEE Trans. Computers, vol. 44, no. 11, pp. 1,296-1,305, Nov. 1995.]]

Digital Library

[22]

C. Stroud S. Konala P. Chen and M. Abramovici, "Built-In-Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST without Overhead!)," Proc. 14th IEEE VLSI Test Symp., 1996.]]

Digital Library

[23]

C. Stroud E. Lee and M. Abramovici, "BIST-Based Diagnostics of FPGA Logic Blocks," Proc. Int'l Test Conf., 1996.]]

Digital Library

[24]

Field-Programmable Gate Array Technology, S. Trimberger, ed. Boston: Kluwer Academic, 1994.]]

Digital Library

[25]

S. Trimberger, Xilinx Corporation, private communication, July 1995.]]

[26]

J. Turner, "FPGA Yield Enhancement through Redundancy," unpublished presentation at Second ACM Inte'l Workshop Field Programmable Gate Arrays, reported in SIGDA Newsletter, vol. 24, nos. 1 /2, pp. 31-36, 1994.]]

Digital Library

[27]

Xilinx, Inc., The Programmable Logic Data Book. 1994.]]

[28]

Private communication with Xilinx engineers when S. Dutt visited Xilinx, Aug. 1996.]]

Cited By

Parris MSharma CDemara R(2011)Progress in autonomous fault recovery of field programmable gate arraysACM Computing Surveys10.1145/1978802.197881043:4(1-30)Online publication date: 18-Oct-2011
https://dl.acm.org/doi/10.1145/1978802.1978810
Lehtonen TWolpert DLiljeberg PPlosila JAmpadu P(2010)Self-adaptive system for addressing permanent errors in on-chip interconnectsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201371118:4(527-540)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2013711
Gericota MAlves GSilva MFerreira J(2008)Reliability and availability in reconfigurable computingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200114116:11(1545-1558)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001141
Show More Cited By

Index Terms

Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
1. Hardware
  1. Hardware test
  2. Robustness

Recommendations

Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
ICCD '96: Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors

Significant increases in chip yield can result if faulty logic cells and wiring in Field Programmable Gate Arrays (FPGAs) can be isolated from the remainder of the circuitry to retain a completely usable chip. Utilizing the principle of node-covering, a ...
Tolerating operational faults in cluster-based FPGAs
FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of ...
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
Special section on the 2001 international conference on computer design (ICCD)

Topics related to the faults in SRAM-based field programmable gate arrays (FPGAs) have been intensively studied in recent research studies. These topics include FPGA fault detection, FPGA fault diagnosis, FPGA defect tolerance, and FPGA fault tolerance. ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 47, Issue 1

January 1998

143 pages

ISSN:0018-9340

Editors:
Jane W. S. Liu
Univ. of Illinois
,
Karama Kanoun
CNRS
,
Irith Pomeranz
Univ. of Iowa, Iowa City

Issue’s Table of Contents

Copyright © © 1998 IEEE.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 January 1998

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

26
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Parris MSharma CDemara R(2011)Progress in autonomous fault recovery of field programmable gate arraysACM Computing Surveys10.1145/1978802.197881043:4(1-30)Online publication date: 18-Oct-2011
https://dl.acm.org/doi/10.1145/1978802.1978810
Lehtonen TWolpert DLiljeberg PPlosila JAmpadu P(2010)Self-adaptive system for addressing permanent errors in on-chip interconnectsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201371118:4(527-540)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2013711
Gericota MAlves GSilva MFerreira J(2008)Reliability and availability in reconfigurable computingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200114116:11(1545-1558)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001141
Uvarov S(2007)Design of the EPLD-based reconfigurable fault-tolerant systems with cell-level redundancyAutomation and Remote Control10.1134/S000511790709017268:9(1631-1642)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1134/S0005117907090172
Emmert JStroud CAbramovici M(2007)Online fault tolerance for FPGA logic blocksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89110215:2(216-226)Online publication date: 1-Feb-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.891102
Omaña MCazeaux JRossi DMetra CGielen G(2006)Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnectsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131533(170-175)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131533
Cheatham JEmmert JBaumgart S(2006)A survey of fault tolerant methodologies for FPGAsACM Transactions on Design Automation of Electronic Systems10.1145/1142155.114216711:2(501-533)Online publication date: 1-Apr-2006
https://dl.acm.org/doi/10.1145/1142155.1142167
Campregher NCheung PConstantinides GVasilko MSchmit HWilton S(2005)Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAsProceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays10.1145/1046192.1046211(138-148)Online publication date: 20-Feb-2005
https://dl.acm.org/doi/10.1145/1046192.1046211
Verma VDutt SSuthar VMalik SFix LKahng A(2004)Efficient on-line testing of FPGAs with provable diagnosabilitiesProceedings of the 41st annual Design Automation Conference10.1145/996566.996705(498-503)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996705
Ko SLo J(2004)Efficient Realization of Parity Prediction Functions in FPGAsJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000042513.15382.e720:5(489-499)Online publication date: 1-Oct-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000042513.15382.e7
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents