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Timing Analysis Using Functional Analysis

Published: 01 October 1988 Publication History

Abstract

The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it could be found that a long path is never activated. This results in more accurate delays. A comparison is made of three arrival time functions, A, B, and R. A is the arrival time as given by exhaustive simulation; B is the arrival time as calculated by a usual block-oriented algorithm; and R is the arrival time, that does functional analysis. It is shown that B contained in R contained in A. The first relation means that R is never more conservative than B and whenever the containment is proper, R is an improvement over B. The second relation means that R is correct in the sense that it will never assert a signal to be valid when it is not valid according to the ideal A. Experimental results showing how often R is an improvement over B are presented.

References

[1]
{1} R. B. Hitchcock, Sr., G. L. Smith, and D. D. Cheng, "Timing analysis of computer hardware," IBM J. Res. Develop., pp. 100-105, Jan. 1982.
[2]
{2} M. A. Breuer and A. D. Friedman, Diagnosis and Reliable Design of Digital Systems. Rockville, MD: Computer Science press, 1976.
[3]
{3} D. Brand, "Redundancy and DON'T CARES in logic synthesis," IEEE Trans. Comput., vol. C-32, Oct. 1983.
[4]
{4} D. Brand and V. S. Iyengar, "Timing analysis using functional analysis," IBM J. Res. Rep., RC 11768, Mar. 1986.
[5]
{5} J. A. Darringer, D. Brand, J. V. Gerbi, W. H. Joyner, Jr., and L. Trevillyan, "LSS: A system for production logic synthesis," IBM J. Res. Develop., vol. 28, Sept. 1984.
[6]
{6} CMOS Macrocell Manual AR50-000001-20 B, LSI Inc.

Cited By

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  • (2001)Static timing analysisLogic Synthesis and Verification10.5555/566845.566859(373-401)Online publication date: 1-Nov-2001
  • (2000)Quality of EDA CAD ToolsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855839Online publication date: 20-Mar-2000
  • (1999)Timing-safe false path removal for combinational modulesProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.340075(544-550)Online publication date: 7-Nov-1999
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Information & Contributors

Information

Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 37, Issue 10
October 1988
165 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 October 1988

Author Tags

  1. arrival time
  2. block-oriented algorithm
  3. functional analysis
  4. logic circuits
  5. logic design
  6. logic testing.
  7. timing analysis

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Cited By

View all
  • (2001)Static timing analysisLogic Synthesis and Verification10.5555/566845.566859(373-401)Online publication date: 1-Nov-2001
  • (2000)Quality of EDA CAD ToolsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855839Online publication date: 20-Mar-2000
  • (1999)Timing-safe false path removal for combinational modulesProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.340075(544-550)Online publication date: 7-Nov-1999
  • (1998)Propagation of last-transition-time constraints in gate-level timing analysisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368418(796-802)Online publication date: 23-Feb-1998
  • (1996)BooleDozerIBM Journal of Research and Development10.1147/rd.404.040740:4(407-430)Online publication date: 1-Jul-1996
  • (1994)Gate-level timing verification using waveform narrowingProceedings of the conference on European design automation10.5555/198174.198287(374-379)Online publication date: 23-Sep-1994
  • (1994)Certified timing verification and the transition delay of a logic circuitIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.3116422:3(333-342)Online publication date: 1-Sep-1994
  • (1992)False loops through resource sharingProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304131(345-348)Online publication date: 8-Nov-1992
  • (1992)The exact solution of timing verificationProceedings of the conference on European design automation10.5555/159754.161742(132-137)Online publication date: 1-Nov-1992
  • (1991)A hierarchical approach to timing verification in CMOS VLSI designProceedings of the conference on European design automation10.5555/951513.951571(266-270)Online publication date: 25-Feb-1991
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