research-article

Built-In Testing of Integrated Circuit Wafers

Authors:

Sampath Rangarajan,

Donald Fussell,

Miroslaw MalekAuthors Info & Claims

IEEE Transactions on Computers, Volume 39, Issue 2

Pages 195 - 205

https://doi.org/10.1109/12.45205

Published: 01 February 1990 Publication History

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Abstract

Production testing of a digital circuit requires the generation of a sequence of tests and their application to the circuit being tested. Currently, in test application, the output of the circuit under test is compared to a known correct output for each test. The method has some drawbacks likely to become more critical in the near future. In homogeneous systems of identical integrated circuits of silicon wafers, testing can be done in another way, i.e. by applying a common test to several processing elements at once and comparing the results produced by them. The authors analyze such schemes and show that they are inherently as accurate as current methods that use assumed correct results for production testing. Since this approach could allow wafers to be tested for production faults significantly more quickly than by using a probe tester, the results indicate that it can provide an attractive alternative to current methods for production testing of silicon wafers.

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Duarte EZiwich RAlbini L(2011)A survey of comparison-based system-level diagnosisACM Computing Surveys10.1145/1922649.192265943:3(1-56)Online publication date: 29-Apr-2011
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Lu XLi JSeo C(2009)Probabilistic diagnosis of clustered faults for shared structuresMathematical and Computer Modelling: An International Journal10.1016/j.mcm.2008.06.01149:3-4(623-634)Online publication date: 1-Feb-2009
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Index Terms

Built-In Testing of Integrated Circuit Wafers
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Very large scale integration design

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Reviews

Reviewer: Scott Davidson

Assume that a wafer contains an array of identical integrated circuits, that a test can be applied to all of these in parallel, and that the test results for each IC can be compared. In the usual case a test is applied and the results are analyzed by some external hardware. This paper proposes that the status of an IC be determined by voting (comparison of the test results) rather than by analysis of the results by external hardware. The probabilities of optimistic (a faulty circuit declared good) and pessimistic (a good circuit declared faulty) results are computed. The fault coverage of the test is factored into this, but is not an issue for the method. The paper covers the issues of wafer-scale testing quite well. One concern, that of communication between wafers, has been met since the submission of the paper by IEEE standard 1149.1 on boundary scan (see Jarwala and Zorian [1] for an application of boundary scan to wafer testing). One weakness of the paper is that I find it hard to imagine how test inputs can be applied to each circuit at speed. Perhaps if built-in self-test were used for stimulus generation and output data compression, wafer testing would be more practical. In summary, I found this an interesting exercise with limited short-term practical value.

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 39, Issue 2

February 1990

133 pages

ISSN:0018-9340

Editor:
Ming T. Liu
Ohio State Univ., Columbus

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IEEE Computer Society

United States

Publication History

Published: 01 February 1990

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https://dl.acm.org/doi/10.1109/TPDS.2016.2524004
Duarte EZiwich RAlbini L(2011)A survey of comparison-based system-level diagnosisACM Computing Surveys10.1145/1922649.192265943:3(1-56)Online publication date: 29-Apr-2011
https://dl.acm.org/doi/10.1145/1922649.1922659
Lu XLi JSeo C(2009)Probabilistic diagnosis of clustered faults for shared structuresMathematical and Computer Modelling: An International Journal10.1016/j.mcm.2008.06.01149:3-4(623-634)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1016/j.mcm.2008.06.011
Caruso AChessa SMaestrini P(2007)Worst-Case Diagnosis Completeness in Regular Graphs under the PMC ModelIEEE Transactions on Computers10.1109/TC.2007.105256:7(917-9249)Online publication date: 1-Jul-2007
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Caruso AChessa SMaestrini PSanti P(2003)Fault-diagnosis of grid structuresTheoretical Computer Science10.1016/S0304-3975(01)00200-6290:2(1149-1174)Online publication date: 2-Jan-2003
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Koppolu SChatterjee A(2001)Hierarchical Diagnosis of Identical Units in a SystemIEEE Transactions on Computers10.1109/12.90899450:2(186-191)Online publication date: 1-Feb-2001
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Abstract

References

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Recommendations

Test Scheduling and Control for VLSI Built-in Self-Test

On the decline of testing efficiency as fault coverage approaches 100%

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