research-article

A Data Compression Technique for Built-In Self-Test

Authors:

S. M. Reddy,

K. K. Saluja,

M. G. KarpovskyAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 9

Pages 1151 - 1156

https://doi.org/10.1109/12.2271

Published: 01 September 1988 Publication History

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Abstract

A data compression technique called self-testable and error-propagating space compression is proposed and analyzed. Faults in a realization of Exclusive-OR and Exclusive-NOR gates are analyzed, and the use of these gates in the design of self-testing and error propagating space compressors is discussed. It is argued that the proposed data-compression technique reduce the hardware complexity in built-in self-test (BIST) logic designs using external tester environments.

References

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A Data Compression Technique for Built-In Self-Test

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 9

September 1988

168 pages

ISSN:0018-9340

Editor:
Ming T. Liu

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IEEE Computer Society

United States

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Published: 01 September 1988

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Bhattacharya SChatterjee A(2006)A DFT Approach for Testing Embedded Systems Using DC SensorsIEEE Design & Test10.1109/MDT.2006.13623:6(464-475)Online publication date: 1-Nov-2006
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Hadjicostis C(2005)Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test VectorsIEEE Transactions on Computers10.1109/TC.2005.18954:12(1614-1627)Online publication date: 1-Dec-2005
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Das SJin CJin LAssaf MPetriu ESahinoglu M(2004)Altera max plus II development environment in fault simulation and test implementation of embeddedProceedings of the 6th international conference on Distributed Computing10.1007/978-3-540-30536-1_39(353-360)Online publication date: 27-Dec-2004
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Bhattacharya BDmitriev AGössel M(2003)Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic OutputIEEE Transactions on Computers10.1109/TC.2003.125286052:12(1646-1651)Online publication date: 1-Dec-2003
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Ding JMoloney DWang X(2000)Aliasing-Free Space and Time Compactions with Limited OverheadProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855889Online publication date: 20-Mar-2000
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Gössel MMorosov ASogomonyan E(1999)A New Totally Error Propagating Compactor for Arbitrary Cores with Digital InterfacesProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836545Online publication date: 26-Apr-1999
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Chakrabarty KMurray BHayes J(1998)Optimal Zero-Aliasing Space Compaction of Test ResponsesIEEE Transactions on Computers10.1109/12.73642747:11(1171-1187)Online publication date: 1-Nov-1998
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An improved output compaction technique for built-in self-test in VLSI circuits

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