research-article

SeaStar Interconnect: Balanced Bandwidth for Scalable Performance

Authors:

Ron Brightwell,

Kevin T. Pedretti,

Keith D. Underwood,

Trammell HudsonAuthors Info & Claims

IEEE Micro, Volume 26, Issue 3

Pages 41 - 57

https://doi.org/10.1109/MM.2006.65

Published: 01 May 2006 Publication History

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Abstract

The SeaStar, a new ASIC from Cray, is a full system-on-chip design that integrates high-speed serial links, a 3D router, and traditional network interface functionality, including an embedded processor in a single chip.

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Huang XF. Ramos ADeng Y(2022)Optimal circulant graphs as low-latency network topologiesThe Journal of Supercomputing10.1007/s11227-022-04396-578:11(13491-13510)Online publication date: 1-Jul-2022
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Deng YGuo MRamos AHuang XXu ZLiu W(2020)Optimal low-latency network topologies for cluster performance enhancementThe Journal of Supercomputing10.1007/s11227-020-03216-y76:12(9558-9584)Online publication date: 1-Dec-2020
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Marts WDosanjh MSchonbein WGrant RBridges P(2019)MPI tag matching performance on ConnectX and ARMProceedings of the 26th European MPI Users' Group Meeting10.1145/3343211.3343224(1-10)Online publication date: 11-Sep-2019
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SeaStar Interconnect: Balanced Bandwidth for Scalable Performance

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Information

Published In

IEEE Micro Volume 26, Issue 3

May 2006

85 pages

ISSN:0272-1732

Issue’s Table of Contents

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 2006

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Huang XF. Ramos ADeng Y(2022)Optimal circulant graphs as low-latency network topologiesThe Journal of Supercomputing10.1007/s11227-022-04396-578:11(13491-13510)Online publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1007/s11227-022-04396-5
Deng YGuo MRamos AHuang XXu ZLiu W(2020)Optimal low-latency network topologies for cluster performance enhancementThe Journal of Supercomputing10.1007/s11227-020-03216-y76:12(9558-9584)Online publication date: 1-Dec-2020
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Larkins DSnyder JDinan J(2019)Accelerated Work StealingProceedings of the 48th International Conference on Parallel Processing10.1145/3337821.3337878(1-10)Online publication date: 5-Aug-2019
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Schonbein WGrant RDosanjh MArnold DTaufer MBalaji PPeña A(2019)INCAProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3295500.3356153(1-13)Online publication date: 17-Nov-2019
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Larkins DSnyder JDinan J(2018)Efficient Runtime Support for a Partitioned Global Logical Address SpaceProceedings of the 47th International Conference on Parallel Processing10.1145/3225058.3225092(1-10)Online publication date: 13-Aug-2018
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Rumley SBahadori MPolster RHammond SCalhoun DWen KRodrigues ABergman K(2017)Optical interconnects for extreme scale computing systemsParallel Computing10.1016/j.parco.2017.02.00164:C(65-80)Online publication date: 1-May-2017
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Larkins DDinan J(2016)Extending a message passing runtime to support partitioned, global logical address spacesProceedings of the First Workshop on Optimization of Communication in HPC10.5555/3018058.3018060(11-16)Online publication date: 13-Nov-2016
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Tampouratzis NMattheakis PPapaefstathiou I(2016)Accelerating Intercommunication in Highly Parallel SystemsACM Transactions on Architecture and Code Optimization10.1145/300571713:4(1-25)Online publication date: 2-Dec-2016
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Evaluating the energy consumption and the silicon area of on-chip interconnect architectures

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