A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation
Pages 1950 - 1959
Abstract
This article presents a current-adjusting auto-zeroing (CAAZ) scheme that overcomes the critical shortcomings of state-of-the-art auto-zero-based offset and low-frequency noise cancellation methods. The proposed technique appropriately adjusts the bias current of individual branches within the amplifier to cancel dc offset and low-frequency noise. The CAAZ method does not suffer from thermal-noise increase due to input signal division and stability issues encountered in input auto-zero (IAZ) or limited allowable gain and input swing experienced in the output auto-zero (OAZ) method. Moreover, it does not create any feedback loop during its operation phases and, thus, does not impose additional stability restrictions on the amplifier within which it is being used. Two differential amplifiers, a single-stage differential amplifier (SSDA) and a folded-cascode amplifier (FCA), employing the proposed CAAZ technique, are designed and simulated in a standard 180-nm CMOS process. Simulation results verify the higher performance of the proposed CAAZ compared to the conventional counterparts.
References
[1]
H. Puet al., “A CMOS BD-BCI incorporating stimulation with dual-mode charge balancing and time-domain pipelined recording,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Jul. 2023, pp. 1–2.
[2]
H. Pu, O. Malekzadeh-Arasteh, A. R. Danesh, Z. Nenadic, A. H. Do, and P. Heydari, “A CMOS dual-mode brain–computer interface chipset with 2-mV precision time-based charge balancing and stimulation-side artifact suppression,” IEEE J. Solid-State Circuits, vol. 57, no. 6, pp. 1824–1840, Jun. 2022.
[3]
F. Tzeng, A. Jahanian, D. Pi, and P. Heydari, “A CMOS code-modulated path-sharing multi-antenna receiver front-end,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1321–1335, May 2009.
[4]
B. Razavi, Design of Analog CMOS Integrated Circuits. New York, NY, USA: Mc-Graw-Hill, 2017.
[5]
A. Bakker, K. Thiele, and J. Huijsing, “A CMOS nested-chopper instrumentation amplifier with 100-nV offset,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1877–1883, Dec. 2000.
[6]
Q. Huang and C. Menolfi, “A 200 nV offset 6.5 nV/vHz noise PSD 5.6 kHz chopper instrumentation amplifier in 1 μm digital CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2001, pp. 362–363.
[7]
C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Jun. 1996.
[8]
M. A. P. Pertijs and W. J. Kindt, “A 140 dB-CMRR current-feedback instrumentation amplifier employing ping-pong auto-zeroing and chopping,” IEEE J. Solid-State Circuits, vol. 45, no. 10, pp. 2044–2056, Oct. 2010.
[9]
T. Rooijers, J. H. Huijsing, and K. A. A. Makinwa, “An auto-zero-stabilized voltage buffer with a quiet chopping scheme and constant sub-pA input current,” IEEE J. Solid-State Circuits, vol. 57, no. 8, pp. 2438–2448, Aug. 2022.
[10]
S. Songet al., “A low-voltage chopper-stabilized amplifier for fetal ECG monitoring with a 1.41 power efficiency factor,” IEEE Trans. Biomed. Circuits Syst., vol. 9, no. 2, pp. 237–247, Apr. 2015.
[11]
B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916–1926, Dec. 1992.
[12]
T. Rooijers, J. H. Huijsing, and K. A. A. Makinwa, “3.2 A chopper-stabilized amplifier with a relaxed fill-in technique and 22.6pA input current,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2023, pp. 2–4.
[13]
C. Enz, “High-precision CMOS amplifiers,” Ph.D. dissertation, Dept. D’electricite, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, 1989.
[14]
Z. Zhou, L. Zhu, W. Wang, J. Li, Q. Meng, and Z. Wang, “A capacitively-coupled chopper instrumentation amplifier with compensated auto-zeroed DC servo-loop for neural signal recording,” IEEE Trans. Circuits Syst. II, Exp. Briefs, early access, Jul. 3, 2023. 10.1109/TCSII.2023.3291375.
[15]
T. Rooijers, J. H. Huijsing, and K. A. A. Makinwa, “A quiet digitally assisted auto-zero-stabilized voltage buffer with 0.6 pA input current and 0.6pV offset,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2018, pp. 50–52.
[16]
A. Tang, “A 3μV offset operational amplifier with 20 nV input noise PSD at DC employing both chopping and autozeroing,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 1, Feb. 2002, pp. 386–387.
[17]
I. E. Opris and G. T. A. Kovacs, “A rail-to-rail ping-pong op-amp,” IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1320–1324, Sep. 1996.
[18]
A. Papoulis and S. U. Pillai, Probability, Random Variables, and Stochastic Processes, 4th ed. Boston, MA, USA: McGraw-Hill, 2002.
[19]
P. Heydari, “Noise analysis of passive sampling mixers using auto- and cross-correlation functions,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2021, pp. 1–5.
[20]
A. R. Danesh, M. Safiallah, H. Pu, and P. Heydari, “An isolated frequency compensation technique for ultra-low-power low-noise two-stage OTAs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, early access, Jul. 26, 2023. 10.1109/TCSII.2023.3298890.
Index Terms
- A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation
Index terms have been assigned to the content through auto-classification.
Recommendations
A high-speed low-power CMOS comparator using auto-zero offset cancellation technique
SBCCI '11: Proceedings of the 24th symposium on Integrated circuits and systems designA high-speed, small-area and accurate CMOS comparator for low-power applications is presented. The comparator consists of an offset cancelled input stage using a new auto-zero technique. In particular, this circuit is suitable for portable applications, ...
A wideband current amplifier with DC-offset cancellation utilizing chopper modulation
A wideband current amplifier with DC-offset cancellation utilizing chopper modulation is proposed. Combining series---series feedback with backgate driven choppers, a wideband current amplifier with DC-offset cancellation is realized. As consumed a ...
A High Gain and Low Flicker Noise CMOS Mixer with Low Flicker Noise Corner Frequency Using Tunable Differential Active Inductor
This paper presents the design of a high conversion gain and low flicker noise down conversion CMOS double balanced Gilbert cell mixer using $$0.18\,\upmu \hbox {m}$$ 0.18 μ m CMOS technology. The high conversion gain and low flicker noise mixer is implemented by using a differential ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
1063-8210 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.
Publisher
IEEE Educational Activities Department
United States
Publication History
Published: 22 September 2023
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 11 Jan 2025