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Dynamic Traffic Regulation in NoC-Based Systems

Authors:

Yuan YaoAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 25, Issue 2

Pages 556 - 569

https://doi.org/10.1109/TVLSI.2016.2584781

Published: 01 February 2017 Publication History

Abstract

In network-on-chip (NoC)-based systems, performance enhancement has primarily focused on the network itself, with little attention paid on controlling traffic injection at the network boundary. This is unsatisfactory because traffic may be over injected, aggravating congestion, and lowering performance. Recently, traffic regulation is proposed as an orthogonal means for performance improvement. Rather than as soon as possible admission, traffic regulation may hold back packet injection by admitting packets into the network only when the accumulated traffic volume at any time interval does not exceed a threshold. These regulation techniques are, however, often static, likely causing overregulation and underregulation. We propose dynamic traffic regulation to improve the system performance for NoC-based multi/many-processor systems-on-chip (MPSoC) and chip multi/many-core processor (CMP) designs. It can be applied to MPSoCs for intellectual property integration in an open-loop fashion by injecting traffic according to its run-time profiled characteristics. It can also be applied to CMPs in a closed-loop fashion by admitting traffic fully adaptive to the traffic and network states. Through extensive experiments and results, we show that both the open-loop and closed-loop dynamic regulation techniques can significantly improve the network and system performance.

References

[1]

K. Olukotun, L. Hammond, and J. Laudon, Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency . San Rafael, CA, USA: Morgan & Claypool Publishers, 2007.

[2]

Z. Lu, M. Millberg, A. Jantsch, A. Bruce, P. van der Wolf, and T. Henriksson, “ Flow regulation for on-chip communication,” in Proc. Design, Autom. Test Europe Conf. Exhibit. (DATE), Nice, France, Apr. 2009, pp. 578–581.

[3]

F. Jafari, Z. Lu, A. Jantsch, and M. H. Yaghmaee, “ Buffer optimization in network-on-chip through flow regulation,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. Volume 29, no. Issue 12, pp. 1973–1986, 2010.

[4]

R. L. Cruz, “ A calculus for network delay, part I: Network elements in isolation,” IEEE Trans. Inf. Theory, vol. Volume 37, no. Issue 1, pp. 114–131, 1991.

Digital Library

[5]

J.-Y. Le Boudec and P. Thiran, Network Calculus: A Theory of Deterministic Queuing Systems for the Internet (Lecture Notes in Computer Science), vol. Volume 2050 . Berlin, Germany: Springer, 2004.

[6]

C.-S. Chang, Performance Guarantees in Communication Networks . London, U.K.: Springer-Verlag, 2000.

[7]

D. Stiliadis and A. Varma, “ Latency-rate servers: A general model for analysis of traffic scheduling algorithms,” IEEE/ACM Trans. Netw., vol. Volume 6, no. Issue 5, pp. 611–624, 1998.

Digital Library

[8]

X. Zhao and Z. Lu, “ Heuristics-aided tightness evaluation of analytical bounds in networks-on-chip,” IEEE Trans. Comput.-Aided Design Integr., vol. Volume 34, no. Issue 6, pp. 986–999, 2015.

[9]

Y. Jiang, “ A basic stochastic network calculus,” ACM SIGCOMM Comput. Commun. Rev., vol. Volume 36, no. Issue 4, pp. 123–134, 2006.

Digital Library

[10]

E. Wandeler, L. Thiele, M. Verhoef, and P. Lieverse, “ System architecture evaluation using modular performance analysis: A case study,” Int. J. Softw. Tools Technol. Transf., vol. Volume 8, no. Issue 6, pp. 649–667, 2006.

[11]

R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst, “ System level performance analysis The SymTA/S approach,” IEE Proc.-Comput. Digit. Techn., vol. Volume 152, no. Issue 2, pp. 148–166, 2005.

[12]

E. Wandeler, A. Maxiaguine, and L. Thiele, “ Performance analysis of greedy shapers in real-time systems,” in Proc. Design, Autom. Test Eur., Mar. 2006, pp. 444–449.

[13]

M. H. Wiggers, M. J. G. Bekooij, and G. J. M. Smit, “ Modelling run-time arbitration by latency-rate servers in dataflow graphs,” in Proc. Int. Workshop Softw. Compil. Embedded Syst. (SCOPES), Apr. 2007, pp. 11–22.

Digital Library

[14]

B. D. de Dinechin, Y. Durand, D. van Amstel, and A. Ghiti, “ Guaranteed services of the NoC of a manycore processor,” in Proc. Int. Workshop Netw. Chip Archit., 2014, pp. 11–16.

Digital Library

[15]

Z. Lu and A. Jantsch, “ TDM virtual-circuit configuration for network-on-chip,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. Volume 16, no. Issue 8, pp. 1021–1034, 2008.

Digital Library

[16]

G. V. Varatkar and R. Marculescu, “ On-chip traffic modeling and synthesis for MPEG-2 video applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. Volume 12, no. Issue 1, pp. 108–118, 2004.

Digital Library

[17]

W. J. Dally and B. P. Towles, Principles and Practices of Interconnection Networks . San Mateo, CA, USA: Morgan Kaufmann, 2004.

Digital Library

[18]

P. Bogdan and R. Marculescu, “ Non-stationary traffic analysis and its implications on multicore platform design,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. Volume 30, no. Issue 4, pp. 508–519, 2011.

Digital Library

[19]

P. Bogdan, M. Kas, R. Marculescu, and O. Mutlu, “ QuaLe: A quantum-leap inspired model for non-stationary analysis of NoC traffic in chip multi-processors,” in Proc. 4th ACM/IEEE Int. Symp. Netw.-Chip (NOCS), May 2010, pp. 241–248.

Digital Library

[20]

A. Bansal, S. Gupta, and T. Majumder, “ Efficient estimation of non-stationary traffic parameters on networks-on-chip,” in Proc. IEEE Int. Parallel Distrib. Process. Symp. Workshop (IPDPSW), May 2015, pp. 425–433.

Digital Library

[21]

U. Y. Ogras and R. Marculescu, Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures (Lecture Notes in Electrical Engineering), vol. Volume 184 . New York, NY, USA: Springer, 2013.

[22]

U. Y. Ogras, P. Bogdan, and R. Marculescu, “ An analytical approach for network-on-chip performance analysis,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. Volume 29, no. Issue 12, pp. 2001–2013, 2010.

[23]

J. L. Henning, “ SPEC CPU2006 benchmark descriptions,” ACM SIGARCH Comput. Archit. News, vol. Volume 34, no. Issue 4, pp. 1–17, 2006.

Digital Library

[24]

X. Chen et al., “ In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches,” ACM Trans. Design Autom. Electron. Syst., vol. Volume 18, no. Issue 4, pp. 47:1–47:21, 2013.

Digital Library

[25]

L. Zadeh, “ Fuzzy sets,” Inf. Control, vol. Volume 8, no. Issue 3, pp. 338–353, 1965.

[26]

Z. Lu and Y. Wang, “ Dynamic flow regulation for IP integration on network-on-chip,” in Proc. Int. Symp. Netw. Chip (NOCS), May 2012, pp. 115–123.

Digital Library

[27]

Y. Yao and Z. Lu, “ Fuzzy flow regulation for network-on-chip based chip multiprocessors systems,” in Proc. 19th Asia South Pacific Design Autom. Conf. (ASPDAC), Singapore, Jan. 2014, pp. 343–348.

[28]

N. Binkert et al., “ The gem5 simulator,” ACM SIGARCH Comput. Archit. News, vol. Volume 39, no. Issue 2, pp. 1–7, 2011.

Digital Library

[29]

C. Bienia, S. Kumar, J. P. Singh, and K. Li, “ The PARSEC benchmark suite: Characterization and architectural implications,” in Proc. Int. Conf. Parallel Archit. Compil. Techn. (PACT), Aug. 2008, pp. 72–81.

Digital Library

[30]

K. M. Passino and S. Yurkovich, Fuzzy Control . Reading, MA, USA: Addison-Wesley, 1997.

[31]

J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 5th ed. San Mateo, CA, USA: Morgan Kaufmann, 2011.

Cited By

Hu XLu Z(2021)A Configurable Hardware Architecture for Runtime Application of Network CalculusInternational Journal of Parallel Programming10.1007/s10766-021-00700-749:5(745-760)Online publication date: 1-Oct-2021
https://dl.acm.org/doi/10.1007/s10766-021-00700-7
Zhang YHong XChen ZPeng ZJiang J(2020)A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/341406026:1(1-26)Online publication date: 27-Oct-2020
https://dl.acm.org/doi/10.1145/3414060
Hu XLu Z(2020)A Configurable Hardware Architecture for Runtime Application of Network CalculusNetwork and Parallel Computing10.1007/978-3-030-79478-1_18(203-216)Online publication date: 28-Sep-2020
https://dl.acm.org/doi/10.1007/978-3-030-79478-1_18
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Dynamic Traffic Regulation in NoC-Based Systems
1. General and reference
  1. Cross-computing tools and techniques

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 25, Issue 2

February 2017

400 pages

ISSN:1063-8210

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Copyright © 2017.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 February 2017

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Cited By

Hu XLu Z(2021)A Configurable Hardware Architecture for Runtime Application of Network CalculusInternational Journal of Parallel Programming10.1007/s10766-021-00700-749:5(745-760)Online publication date: 1-Oct-2021
https://dl.acm.org/doi/10.1007/s10766-021-00700-7
Zhang YHong XChen ZPeng ZJiang J(2020)A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/341406026:1(1-26)Online publication date: 27-Oct-2020
https://dl.acm.org/doi/10.1145/3414060
Hu XLu Z(2020)A Configurable Hardware Architecture for Runtime Application of Network CalculusNetwork and Parallel Computing10.1007/978-3-030-79478-1_18(203-216)Online publication date: 28-Sep-2020
https://dl.acm.org/doi/10.1007/978-3-030-79478-1_18
Wang BLu ZChen S(2019)ANN Based Admission Control for On-Chip NetworksProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317772(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317772
Lu ZZhao X(2018)xMAS-Based QoS Analysis MethodologyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.270656137:2(364-377)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TCAD.2017.2706561

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