research-article

Fault Tolerant Parallel Filters Based on Error Correction Codes

Authors:

Juan Antonio MaestroAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 23, Issue 2

Pages 384 - 387

https://doi.org/10.1109/TVLSI.2014.2308322

Published: 01 February 2015 Publication History

Abstract

Digital filters are widely used in signal processing and communication systems. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that exploit the filters' structure and properties to achieve fault tolerance have been proposed. As technology scales, it enables more complex systems that incorporate many filters. In those complex systems, it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC. This new scheme allows more efficient protection when the number of parallel filters is large. The technique is evaluated using a case study of parallel finite impulse response filters showing the effectiveness in terms of protection and implementation cost.

References

[1]

M. Nicolaidis, “Design for soft error mitigation,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 405–418, Sep. 2005.

Crossref

Google Scholar

[2]

A. Reddy and P. Banarjee “Algorithm-based fault detection for signal processing applications,” IEEE Trans. Comput., vol. 39, no. 10, pp. 1304–1308, Oct. 1990.

Digital Library

Google Scholar

[3]

B. Shim and N. Shanbhag, “Energy-efficient soft error-tolerant digital signal processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336–348, Apr. 2006.

Digital Library

Google Scholar

[4]

T. Hitana and A. K. Deb, “Bridging concurrent and non-concurrent error detection in FIR filters,” in Proc. Norchip Conf., 2004, pp. 75–78.

Google Scholar

[5]

Y.-H. Huang, “High-efficiency soft-error-tolerant digital signal processing using fine-grain subword-detection processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 291–304, Feb. 2010.

Digital Library

Google Scholar

[6]

S. Pontarelli, G. C. Cardarilli, M. Re, and A. Salsano, “Totally fault tolerant RNS based FIR filters,” in Proc. IEEE IOLTS, Jul. 2008, pp. 192–194.

Google Scholar

[7]

Z. Gao, W. Yang, X. Chen, M. Zhao, and J. Wang, “Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design,” in Proc. IEEE IOLTS, Jun. 2012, pp. 130–133.

Google Scholar

[8]

P. Reviriego, C. J. Bleakley, and J. A. Maestro, “Strutural DMR: A technique for implementation of soft-error-tolerant FIR filters,” IEEE Trans. Circuits Syst., Exp. Briefs, vol. 58, no. 8, pp. 512–516, Aug. 2011.

Crossref

Google Scholar

[9]

P. P. Vaidyanathan. Multirate Systems and Filter Banks. Upper Saddle River, NJ, USA: Prentice-Hall, 1993.

Digital Library

Google Scholar

[10]

A. Sibille, C. Oestges, and A. Zanella, MIMO: From Theory to Implementation. San Francisco, CA, USA: Academic Press, 2010.

Digital Library

Google Scholar

[11]

P. Reviriego, S. Pontarelli, C. Bleakley, and J. A. Maestro, “Area efficient concurrent error detection and correction for parallel filters,” IET Electron. Lett., vol. 48, no. 20, pp. 1258–1260, Sep. 2012.

Google Scholar

[12]

A. V. Oppenheim and R. W. Schafer, Discrete Time Signal Processing. Upper Saddle River, NJ, USA: Prentice-Hall 1999.

Google Scholar

[13]

S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall. 2004.

Digital Library

Google Scholar

[14]

R. W. Hamming, “Error correcting and error detecting codes,” Bell Syst. Tech. J., vol. 29, pp. 147–160, Apr. 1950.

Crossref

Google Scholar

Cited By

View all

Savalam CAlapati V(2023)Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applicationsSoft Computing - A Fusion of Foundations, Methodologies and Applications10.1007/s00500-022-07371-727:7(4289-4306)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1007/s00500-022-07371-7
Gao ZReviriego PXu ZSu XZhao MWang JMaestro J(2016)Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval ChecksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.240862124:2(769-773)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2408621

Index Terms

Fault Tolerant Parallel Filters Based on Error Correction Codes

Index terms have been assigned to the content through auto-classification.

Recommendations

Fault Tolerant Single Error Correction Encoders

Soft errors are an important issue for circuit reliability. To mitigate their effects on the system functionality, different techniques are used. In many cases Error Correcting Codes (ECC) are used to protect circuits. Single Error Correction (SEC) ...
An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads
Abstract
Importance of Error Correcting Codes (ECCs) is increasing rapidly for protecting memories from localized errors. These localized errors in memories are mainly due to radiation induced soft errors which corrupt data stored in a single cell or ...
Totally Fault Tolerant RNS Based FIR Filters
IOLTS '08: Proceedings of the 2008 14th IEEE International On-Line Testing Symposium

In this paper, the design of a Finite Impulse Response (FIR) filter with fault tolerant capabilities based on the residue number system is analyzed. Differently from other approaches that use RNS, the filter implementation is fault tolerant not only ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 23, Issue 2

Feb. 2015

192 pages

ISSN:1063-8210

Issue’s Table of Contents

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 February 2015

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 11 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Savalam CAlapati V(2023)Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applicationsSoft Computing - A Fusion of Foundations, Methodologies and Applications10.1007/s00500-022-07371-727:7(4289-4306)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1007/s00500-022-07371-7
Gao ZReviriego PXu ZSu XZhao MWang JMaestro J(2016)Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval ChecksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.240862124:2(769-773)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2408621

Abstract

References

Cited By

Index Terms

Recommendations

Fault Tolerant Single Error Correction Encoders

An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads

Totally Fault Tolerant RNS Based FIR Filters

Comments

Information

Published In

Publisher

Publication History

Author Tags

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations