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View all- Biswas D(2022)Spur Reduction Circuit for Fractional-N PLLsCircuits, Systems, and Signal Processing10.1007/s00034-021-01900-941:5(2466-2485)Online publication date: 1-May-2022
A 3 GHz wideband ΣΔ fractional-N synthesizer with switched-RC sample-and-hold PFD
Pages 1681 - 1690
Abstract
Designing high linearity phase-frequency-detectors (PFDs) in low-voltage, deep submicrometer processes is a challenging problem. Nonlinear PFDs can fold out of band phase noise, and increase in-band phase noise of fractional-N PLLs in deep submicron processes. A 3-GHz Type-I ΣΔ fractional-N PLL with an exponentially settling voltage-mode switched-RC phase frequency detector (PFD) is presented. A voltage-mode, fully settled switched-RC (SRC)-based sample-and-hold PFD, providing benefits of both an RC loop-filter and a zero-order hold sinc() suppressing reference clock leakage is presented. The exponentially settled SRC PFD is shown to reduce the in-band leakage of quantization noise by 13 dB in comparison to a similar current-mode charge pump PFD, enabling a measured loop-bandwidth of 890-kHz. The fractional-N PLL is fabricated in a 180-nm CMOS technology with 6 metal layers and consumes 18-mA from a 1.8-V power supply. The worst-case near-integer in-band spur is measured at -62 dBc. The measured in-band phase noise at 100-kHz offset from the 3-GHz carrier is -107 dBc/Hz and out-of-band phase noise at 3-MHz offset is -130 dBc/Hz. The phase-locked loop settling time for a frequency step of 45-MHz and 0.1-ppm accuracy is less than 10-µs.
References
[1]
H. Hedayati, W. Khalil, and B. Bakkaloglu, "A 1 MHz bandwidth, 6 GHz 0.18 µm CMOS type-I ΔΣ fractional-N synthesizer for WiMAX applications," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3244-3252, Dec. 2009.
[2]
B. Bisla, R. Eline, and L. M. Franca-Neto, "RF system and circuit challenges for WiMAXs," Intel Technol. J., vol. 08, no. 03, pp. 189-200, Aug. 2004.
[3]
T. Pollet, M. Van Blade, and M. Moeneclaey, "BER sensitivity of OFDM systems to carrier frequency offset and Wiener phase noise," IEEE Trans. Commun., vol. COM-43, no. 2, pp. 191-193, Feb. 1995.
[4]
H. Hedayati, B. Bakkaloglu, and W. Khalil, "Closed loop nonlinear modeling of wideband ΣΔ fractional-N frequency synthesizers," IEEE Trans. Microw. Theory Tech., vol. 54, no. 10, pp. 302-315, 3654-3663, Oct. 2006.
[5]
T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-Sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, no. 9, pp. 53-559, Sep. 1993.
[6]
T. A. D. Riley, N. M. Filiol, D. Qinghong, and J. Kostamovaara, "Techniques for in-band phase noise reduction in ΣΔ synthesizers," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no. 11, pp. 794-803, Nov. 2003.
[7]
E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, "A 700-KHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications," IEEE J. Solid-State Circuits, pp. 1446-1454, Sep. 2004.
[8]
S. E. Meninger and M. H. Perrott, "A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no. 11, pp. 839-849, Nov. 2003.
[9]
K. J. Wang, A. Swaminathan, and I. Galton, "Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2787-2797, Dec. 2008.
[10]
M. Gupta and B.-S. Song, "A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2842-2851, Dec. 2006.
[11]
Y. Sun, W. Rhee, Z. Wang, and X. Yu, "An FIR-embedded noise filtering method for fractional-N PLL clock generators," IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2426-2436, Sep. 2009.
[12]
H. Hedayati and B. Bakkaloglu, "A 3 GHz wideband ΣΔ fractional-N synthesizer with voltage-mode exponential CP-PFD," in Proc. IEEE Radio Freq. Integr. Circuits Symp., 2009, pp. 325-328.
[13]
G. Ahn, D. Chang, M. Brown, N. Ozaki, H. Youra, K. Yamamura, K. Hamashita, K. Takasuka, G. C. Temes, and U. Moon, "A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398-2407, Dec. 2005.
[14]
F. M. Gardner, "Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, no. 11, pp. 1849-1858, Nov. 1980.
[15]
K. Doris, A. van Roermund, and D. Leenaerts, "A general analysis on the timing jitter in D/A converters," in Proc. ISCAS, 2002, vol. 1, pp. I-117-I-120.
[16]
R. Schreier and G. C. Temes, Delta Sigma Data Converters. Piscataway, NJ: Wiley, 2005.
[17]
A. Berny, A. Niknejad, and R. G. Meyer, "A 1.8 GHz LC VCO with 1.3 GHz tuning range and mixed-signal amplitude calibration," in Proc. IEEE VLSI Circuits Conf., 2004, pp. 54-57.
[18]
E. Hegazi, "An algorithm for automatic tuning of PLLs," in Proc. ISCAS, 2007, pp. 2260-2263.
[19]
H.-Y. Jian, Z. Xu, Y.-C. Wu, and M.-C. F. Chang, "A fractional-N PLL for multiband (0.8-6 GHz) communications using binary weighted D/A differentiator and offset-frequency ΔΣ modulator," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 768-780, Apr. 2010.
[20]
M. H. Perrott, S. Pamarti, E. Hoffman, F. S. Lee, S. Mukherjee, C. Lee, V. Tsinker, S. Perumal, B. Soto, N. Arumugam, and B. W. Garlepp, "A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator," in ISSCC Dig. Tech. Papers, 2010, pp. 244-245.
[21]
B. Zhang, P. E. Allen, and J. M. Huard, "A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-µm," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 855-865, Jun. 2003.
[22]
R. J. Baker, CMOS Mixed-Signal Circuit Design. Piscataway, NJ: IEEE Press, 2003.
- A 3 GHz wideband ΣΔ fractional-N synthesizer with switched-RC sample-and-hold PFD
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Publication History
Published: 01 September 2012
Accepted: 13 June 2011
Revised: 11 April 2011
Received: 08 November 2010
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View all- Biswas D(2022)Spur Reduction Circuit for Fractional-N PLLsCircuits, Systems, and Signal Processing10.1007/s00034-021-01900-941:5(2466-2485)Online publication date: 1-May-2022