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research-article

Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture

Authors:

Yang MengfeiAuthors Info & Claims

IEEE Transactions on Evolutionary Computation, Volume 22, Issue 6

Pages 949 - 960

https://doi.org/10.1109/TEVC.2017.2779874

Published: 01 December 2018 Publication History

Abstract

With the continuous development of computer and electronics, the idea of artificial intelligence has been integrating into the fault tolerance research. As a valuable and prospective intelligent fault tolerance technique in high reliability and high safety applications, the evolvable hardware fault tolerance technique is becoming an important and widely applicable method. However, this technique confronts two difficult problems: evolved circuit scale and evolution efficiency. Toward these problems, we present a programmable architecture called neural network architecture-based virtual reconfigurable circuit (NNA-VRC), and an evolutionary fault tolerance method based on this programmable architecture. The NNA-VRC-based evolution method simplifies the structure and configuration of programmable architecture, avoids illegal interconnections during the circuit evolution, and implements high level (module level) evolution. The experiments of this paper show that a function module scale circuit is evolved efficiently. Furthermore, NNA-VRC-based evolution method can recovery from many injected fault patterns, behaving a strong feature of fault tolerance.

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Cited By

Kumar Sakali RMahammad Shak N(2023)Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction AlgorithmJournal of Electronic Testing: Theory and Applications10.1007/s10836-023-06050-139:1(111-122)Online publication date: 1-Feb-2023
https://dl.acm.org/doi/10.1007/s10836-023-06050-1
Li L(2021)An Online Arrangement Method of Difficult Actions in Competitive Aerobics Based on Multimedia TechnologySecurity and Communication Networks10.1155/2021/99684012021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/9968401

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Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture

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cover image IEEE Transactions on Evolutionary Computation

IEEE Transactions on Evolutionary Computation Volume 22, Issue 6

Dec. 2018

155 pages

ISSN:1089-778X

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1089-778X © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Published: 01 December 2018

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Cited By

Kumar Sakali RMahammad Shak N(2023)Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction AlgorithmJournal of Electronic Testing: Theory and Applications10.1007/s10836-023-06050-139:1(111-122)Online publication date: 1-Feb-2023
https://dl.acm.org/doi/10.1007/s10836-023-06050-1
Li L(2021)An Online Arrangement Method of Difficult Actions in Competitive Aerobics Based on Multimedia TechnologySecurity and Communication Networks10.1155/2021/99684012021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/9968401

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