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research-article

An analytical approach for network-on-chip performance analysis

Authors:

Radu MarculescuAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 29, Issue 12

Pages 2001 - 2013

https://doi.org/10.1109/TCAD.2010.2061613

Published: 01 December 2010 Publication History

Abstract

Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

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Cited By

Li CNasr-Esfahany AZhao KNoorbakhsh KGoyal PAlizadeh MAnderson TSekar VYu MSeneviratne AVeitch D(2024)m3: Accurate Flow-Level Performance Estimation using Machine LearningProceedings of the ACM SIGCOMM 2024 Conference10.1145/3651890.3672243(813-827)Online publication date: 4-Aug-2024
https://dl.acm.org/doi/10.1145/3651890.3672243
Patra RMaji PSrivastava DMondal H(2024)Machine learning-driven performance assessment of network-on-chip architecturesThe Journal of Supercomputing10.1007/s11227-024-06340-180:16(24483-24519)Online publication date: 1-Nov-2024
https://dl.acm.org/doi/10.1007/s11227-024-06340-1
Cardona JHernández CAbella JMezzetti ECazorla F(2023)Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/358200628:3(1-34)Online publication date: 3-Apr-2023
https://dl.acm.org/doi/10.1145/3582006
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An analytical approach for network-on-chip performance analysis
1. General and reference
  1. Cross-computing tools and techniques

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Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 29, Issue 12

December 2010

208 pages

ISSN:0278-0070

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Copyright © 2010.

Publisher

IEEE Press

Publication History

Published: 01 December 2010

Accepted: 12 July 2010

Revised: 15 February 2010

Received: 19 October 2009

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Cited By

Li CNasr-Esfahany AZhao KNoorbakhsh KGoyal PAlizadeh MAnderson TSekar VYu MSeneviratne AVeitch D(2024)m3: Accurate Flow-Level Performance Estimation using Machine LearningProceedings of the ACM SIGCOMM 2024 Conference10.1145/3651890.3672243(813-827)Online publication date: 4-Aug-2024
https://dl.acm.org/doi/10.1145/3651890.3672243
Patra RMaji PSrivastava DMondal H(2024)Machine learning-driven performance assessment of network-on-chip architecturesThe Journal of Supercomputing10.1007/s11227-024-06340-180:16(24483-24519)Online publication date: 1-Nov-2024
https://dl.acm.org/doi/10.1007/s11227-024-06340-1
Cardona JHernández CAbella JMezzetti ECazorla F(2023)Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/358200628:3(1-34)Online publication date: 3-Apr-2023
https://dl.acm.org/doi/10.1145/3582006
Mandal SNarayana SAyoub RKishinevsky MAbousamra AOgras U(2023)Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite BuffersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.325066231:5(670-683)Online publication date: 16-Mar-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3250662
Adusumilli VTG V(2023)Traffic Characterization Based Stochastic Modelling of Network-on-ChipIEEE Transactions on Computers10.1109/TC.2022.319196572:4(1215-1222)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TC.2022.3191965
Krayem IMercier RKillian CKritikakou AChillet DTeuscher CHan J(2022)Data and Fault Aware Routing Algorithm for NoC Based Approximate ComputingProceedings of the 17th ACM International Symposium on Nanoscale Architectures10.1145/3565478.3572327(1-6)Online publication date: 7-Dec-2022
https://dl.acm.org/doi/10.1145/3565478.3572327
Bhaskar V(2021)A Study of Network-on-Chip PerformanceProceedings of the 2021 Thirteenth International Conference on Contemporary Computing10.1145/3474124.3474129(37-42)Online publication date: 5-Aug-2021
https://dl.acm.org/doi/10.1145/3474124.3474129
Krishnan GMandal SChakrabarti CSeo JOgras UCao Y(2021)Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural NetworksACM Journal on Emerging Technologies in Computing Systems10.1145/346023318:2(1-22)Online publication date: 31-Dec-2021
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Mandal STong JAyoub RKishinevsky MAbousamra AOgras U(2021)Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643448(1-9)Online publication date: 1-Nov-2021
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Sambangi RManghnani HChattopadhyay S(2021)LPNetMicroprocessors & Microsystems10.1016/j.micpro.2021.10437087:COnline publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.micpro.2021.104370
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