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research-article

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification

Published: 01 August 2018 Publication History

Abstract

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

Cited By

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  • (2024)TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architecturesThe Journal of Supercomputing10.1007/s11227-023-05700-780:5(6311-6335)Online publication date: 1-Mar-2024
  • (2023)AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2023.324826072:8(2278-2292)Online publication date: 1-Aug-2023
  • (2022)KARL: A Cost-effective Routing Algorithm in Fault Tolerant 3D Network-on-Chip via K-means Assisted Reinforcement LearningProceedings of the 7th International Conference on Big Data and Computing10.1145/3545801.3545808(45-50)Online publication date: 27-May-2022
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Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 67, Issue 8
Aug. 2018
155 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 August 2018

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Cited By

View all
  • (2024)TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architecturesThe Journal of Supercomputing10.1007/s11227-023-05700-780:5(6311-6335)Online publication date: 1-Mar-2024
  • (2023)AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2023.324826072:8(2278-2292)Online publication date: 1-Aug-2023
  • (2022)KARL: A Cost-effective Routing Algorithm in Fault Tolerant 3D Network-on-Chip via K-means Assisted Reinforcement LearningProceedings of the 7th International Conference on Big Data and Computing10.1145/3545801.3545808(45-50)Online publication date: 27-May-2022
  • (2021)AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586174(67-72)Online publication date: 5-Dec-2021
  • (2019)FL-RuNS: A High-Performance and Runtime Reconfigurable Fault-Tolerant Routing Scheme for Partially Connected Three-Dimensional Networks on ChipIEEE Transactions on Nanotechnology10.1109/TNANO.2019.293127118(806-818)Online publication date: 1-Jan-2019
  • (2019)A Plan B for Plan S?IEEE Pervasive Computing10.1109/MPRV.2019.292114218:2(4-7)Online publication date: 9-Aug-2019

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