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research-article

A Customized Processor for Energy Efficient Scientific Computing

Published: 01 December 2012 Publication History

Abstract

The rapid advancements in the computational capabilities of the graphics processing unit (GPU) as well as the deployment of general programming models for these devices have made the vision of a desktop supercomputer a reality. It is now possible to assemble a system that provides several TFLOPs of performance on scientific applications for the cost of a high-end laptop computer. While these devices have clearly changed the landscape of computing, there are two central problems that arise. First, GPUs are designed and optimized for graphics applications resulting in delivered performance that is far below peak for more general scientific and mathematical applications. Second, GPUs are power hungry devices that often consume 100-300 watts, which restricts the scalability of the solution and requires expensive cooling. To combat these challenges, this paper presents the PEPSC architecture—an architecture customized for the domain of data parallel dense matrix style scientific application where power efficiency is the central focus. PEPSC utilizes a combination of a 2D single-instruction multiple-data (SIMD) datapath, an intelligent dynamic prefetching mechanism, and a configurable SIMD control approach to increase execution efficiency over conventional GPUs. A single PEPSC core has a peak performance of 120 GFLOPs while consuming 2 W of power when executing modern scientific applications, which represents an increase in computation efficiency of more than 10X over existing GPUs.

Cited By

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  • (2018)Exploiting architectural features of a computer vision platform towards reducing memory stallsJournal of Real-Time Image Processing10.1007/s11554-018-0830-817:4(853-870)Online publication date: 9-Oct-2018
  • (2016)Improving energy-efficiency of large-scale workflows in heterogeneous systemsInternational Journal of Computational Science and Engineering10.1504/IJCSE.2016.07893213:3(258-267)Online publication date: 1-Jan-2016
  • (2013)Instruction set extensions for dynamic time warpingProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555710(1-10)Online publication date: 29-Sep-2013

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Information & Contributors

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Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 61, Issue 12
December 2012
158 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 2012

Author Tags

  1. Benchmark testing
  2. Computer architecture
  3. Energy efficiency
  4. Energy management
  5. Graphics Processing Unit (GPU)
  6. Graphics processing unit
  7. Low power electronics
  8. Low-power design
  9. Parallel processing
  10. SIMD processors
  11. hardware
  12. parallel processors
  13. processor architectures
  14. scientific computing
  15. throughput computing

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Cited By

View all
  • (2018)Exploiting architectural features of a computer vision platform towards reducing memory stallsJournal of Real-Time Image Processing10.1007/s11554-018-0830-817:4(853-870)Online publication date: 9-Oct-2018
  • (2016)Improving energy-efficiency of large-scale workflows in heterogeneous systemsInternational Journal of Computational Science and Engineering10.1504/IJCSE.2016.07893213:3(258-267)Online publication date: 1-Jan-2016
  • (2013)Instruction set extensions for dynamic time warpingProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555710(1-10)Online publication date: 29-Sep-2013

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