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A Management Strategy for the Reliability and Performance Improvement of MLC-Based Flash-Memory Storage Systems

Published: 01 March 2011 Publication History

Abstract

Cost has been a major driving force in the development of the flash-memory technology. Because of this, serious challenges are now faced for future products on reliability and performance requirements. In this work, we propose a management strategy to resolve the reliability and performance problems of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of advanced multilevel cell flash-memory chips. The capability of the proposed approach is analyzed with reliability considerations and evaluated by experiments over realistic workloads with respect to the reliability and performance improvement.

Cited By

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  • (2021)Optimizing Lifetime Capacity and Read Performance of Bit-Alterable 3-D NAND FlashIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.299878140:2(218-231)Online publication date: 1-Feb-2021
  • (2019)The Best of Both WorldsProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317922(1-6)Online publication date: 2-Jun-2019
  • (2019)A new sequential-write-constrained cache management to mitigate write amplification for SMR drivesProceedings of the 34th ACM/SIGAPP Symposium on Applied Computing10.1145/3297280.3297336(599-606)Online publication date: 8-Apr-2019
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Information

Published In

cover image IEEE Transactions on Computers
IEEE Transactions on Computers  Volume 60, Issue 3
March 2011
142 pages

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 March 2011

Author Tags

  1. Flash-memory management software
  2. Flash-memory management software, disposable flash memory, MLC flash memory, performance enhancement, reliability enhancement, address translation, update commitment.
  3. MLC flash memory
  4. address translation
  5. disposable flash memory
  6. performance enhancement
  7. reliability enhancement
  8. update commitment.

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Cited By

View all
  • (2021)Optimizing Lifetime Capacity and Read Performance of Bit-Alterable 3-D NAND FlashIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.299878140:2(218-231)Online publication date: 1-Feb-2021
  • (2019)The Best of Both WorldsProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317922(1-6)Online publication date: 2-Jun-2019
  • (2019)A new sequential-write-constrained cache management to mitigate write amplification for SMR drivesProceedings of the 34th ACM/SIGAPP Symposium on Applied Computing10.1145/3297280.3297336(599-606)Online publication date: 8-Apr-2019
  • (2019)HyFAT: Affordable Hybrid Fast Address Translating Device Driver for Multichannel-Based Flash DevicesIEEE Transactions on Consumer Electronics10.1109/TCE.2019.290430465:2(142-149)Online publication date: 22-Apr-2019
  • (2019)RFTLCluster Computing10.1007/s10586-018-2824-522:1(25-41)Online publication date: 1-Mar-2019
  • (2018)A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND FlashIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2018.285608026:11(2322-2334)Online publication date: 1-Nov-2018
  • (2016)An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage SystemsACM Transactions on Design Automation of Electronic Systems10.1145/294765822:1(1-22)Online publication date: 13-Dec-2016
  • (2016)A Cache-Based Flash Translation Layer for TLC-Based Multimedia Storage DevicesACM Transactions on Embedded Computing Systems10.1145/282061415:1(1-28)Online publication date: 13-Jan-2016
  • (2016)Retention Trimming for Lifetime Improvement of Flash Memory Storage SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.245336935:1(58-71)Online publication date: 1-Jan-2016
  • (2016)Disturbance Relaxation for 3D Flash MemoryIEEE Transactions on Computers10.1109/TC.2015.245166065:5(1467-1483)Online publication date: 1-May-2016
  • Show More Cited By

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