research-article

On Redundancy and Fault Detection in Sequential Circuits

Authors:

M. Abramovici,

M. A. BreuerAuthors Info & Claims

IEEE Transactions on Computers, Volume 28, Issue 11

Pages 864 - 865

https://doi.org/10.1109/TC.1979.1675267

Published: 01 November 1979 Publication History

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Abstract

In this correspondence we show that the well-known concepts of redundancy and undetectability of a stuck-at fault, which are equivalent in combinational circuits, are not equivalent in sequential circuits. We also show that some faults in sequential circuits, which are undetectable (by "conventional" methods of testing), are detectable by transition count testing methods.

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Keim MDrechsler NDrechsler RBecker B(2001)Combining GAs and Symbolic Methods for High Quality Tests of Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:101119372582417:1(37-51)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1023/A%3A1011193725824
Long DIyer MAbramovici M(2000)FILL and FUNIACM Transactions on Design Automation of Electronic Systems10.1145/348019.3483115:3(631-657)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.1145/348019.348311
Butler K(1999)A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods DataProceedings of the 1999 IEEE International Test Conference10.5555/518925.939345Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939345
Show More Cited By

On Redundancy and Fault Detection in Sequential Circuits
1. Computer systems organization
2. Hardware

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 28, Issue 11

November 1979

74 pages

ISSN:0018-9340

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IEEE Computer Society

United States

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Published: 01 November 1979

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Keim MDrechsler NDrechsler RBecker B(2001)Combining GAs and Symbolic Methods for High Quality Tests of Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:101119372582417:1(37-51)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1023/A%3A1011193725824
Long DIyer MAbramovici M(2000)FILL and FUNIACM Transactions on Design Automation of Electronic Systems10.1145/348019.3483115:3(631-657)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.1145/348019.348311
Butler K(1999)A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods DataProceedings of the 1999 IEEE International Test Conference10.5555/518925.939345Online publication date: 28-Sep-1999
https://dl.acm.org/doi/10.5555/518925.939345
Becker BKeim MKrieger R(1999)Hybrid Fault Simulation for Synchronous Sequential CircuitsJournal of Electronic Testing: Theory and Applications10.1023/A:100837652245115:3(219-238)Online publication date: 1-Dec-1999
https://dl.acm.org/doi/10.1023/A%3A1008376522451
Krieger RBecker BKeim MPreas B(1995)Symbolic fault simulation for sequential circuits and the multiple observation time test strategyProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217552(339-344)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217552
Krieger RBecker BKeim M(1994)A hybrid fault simulator for synchronous sequential circuitsProceedings of the 1994 international conference on Test10.5555/1895949.1896052(614-623)Online publication date: 2-Oct-1994
https://dl.acm.org/doi/10.5555/1895949.1896052
Abramovici MBreuer M(1982)Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause AnalysisIEEE Transactions on Computers10.1109/TC.1982.167594031:12(1165-1172)Online publication date: 1-Dec-1982
https://dl.acm.org/doi/10.1109/TC.1982.1675940

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Does retiming affect redundancy in sequential circuits?

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