T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving

New memory interconnect technology, such as Intel&#x0027;s Compute Express Link (CXL), helps to expand memory bandwidth and capacity by adding CPU-less NUMA nodes to the main memory system, addressing the growing memory wall challenge. Consequently, modern computing systems embrace the heterogeneity in memory systems, composing the memory systems with a tiered memory system with near and far memory (e.g., local DRAM and CXL-DRAM). However, adopting NUMA interleaving, which can improve performance by exploiting node-level parallelism and utilizing aggregate bandwidth, to the tiered memory systems can face challenges due to differences in the access latency between the two types of memory, leading to potential performance degradation for memory-intensive workloads. By tackling the challenges, we first investigate the effects of the NUMA interleaving on the performance of the tiered memory systems. We observe that while NUMA interleaving is essential for applications demanding high memory bandwidth, it can negatively impact the performance of applications demanding low memory bandwidth. Next, we propose a dynamic cache management, called <monospace>T-CAT</monospace>, which partitions the last-level cache between near and far memory, aiming to mitigate performance degradation by accessing far memory. <monospace>T-CAT</monospace> attempts to reduce the difference in the average access latency between near and far memory by re-sizing the cache partitions. Through dynamic cache management, <monospace>T-CAT</monospace> can preserve the performance benefits of NUMA interleaving while mitigating performance degradation by the far memory accesses. Our experimental results show that <monospace>T-CAT</monospace> improves performance by up to 17&#x0025; compared to cases with NUMA interleaving without the cache management.