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research-article

A Case for Speculative Strength Reduction

Published: 01 January 2021 Publication History

Abstract

Most high performance general purpose processors leverage register renaming to implement optimizations such as move elimination or zero-idiom elimination. Those optimizations can be seen as forms of strength reduction whereby a faster but semantically equivalent operation is substituted to a slower operation. In this letter, we argue that other reductions can be performed dynamically if input values of instructions are known in time, i.e., prior to renaming. We study the potential for leveraging Value Prediction to achieve that goal and show that in SPEC2k17, an average of 3.3 percent (up to 6.8 percent) of the dynamic instructions could dynamically be strength reduced. Our experiments suggest that a state-of-the-art value predictor allows to capture 59.7 percent of that potential on average (up to 99.6 percent).

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  • (2021)Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction PotentialMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480050(792-803)Online publication date: 18-Oct-2021

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Published In

cover image IEEE Computer Architecture Letters
IEEE Computer Architecture Letters  Volume 20, Issue 1
Jan.-June 2021
36 pages

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IEEE Computer Society

United States

Publication History

Published: 01 January 2021

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  • (2021)Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction PotentialMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480050(792-803)Online publication date: 18-Oct-2021

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