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View all- Liu BChen GYang BNakatake S(2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
- Wu PLin MLi XHo T(2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
- Wu PLin MLi XHo TDavoodi AYoung E(2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015