[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1109/ISVLSI.2006.47guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
Article

Formulating the Empirical Strategies in Module Generation of Analog MOS Layout

Published: 02 March 2006 Publication History

Abstract

In module generation for analog cell layout, it is necessary to incorporate the designers' empirical techniques to achieve small area as well as high performance. This paper presents the formulation of two types of module generation problems, faithful to expert's empirical knowledge, to ease such incorporation. One is series module generation problem, where we introduce equivalent circuit modif ications to maximize the dif fusion merging and minimize the number of dif fusion contacts. The other is the common-centroid module generation problem which is formulated as a mathematical optimization problem taking coincidence, symmetry, dispersion and compactness into consideration. A greedy algorithm is also presented to solve this problem.

Cited By

View all
  • (2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
  • (2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
  • (2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015

Index Terms

  1. Formulating the Empirical Strategies in Module Generation of Analog MOS Layout

          Recommendations

          Comments

          Please enable JavaScript to view thecomments powered by Disqus.

          Information & Contributors

          Information

          Published In

          cover image Guide Proceedings
          ISVLSI '06: Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
          March 2006
          ISBN:0769525334

          Publisher

          IEEE Computer Society

          United States

          Publication History

          Published: 02 March 2006

          Qualifiers

          • Article

          Contributors

          Other Metrics

          Bibliometrics & Citations

          Bibliometrics

          Article Metrics

          • Downloads (Last 12 months)0
          • Downloads (Last 6 weeks)0
          Reflects downloads up to 05 Jan 2025

          Other Metrics

          Citations

          Cited By

          View all
          • (2018)Routable and Matched Layout Styles for Analog Module GenerationACM Transactions on Design Automation of Electronic Systems10.1145/318216923:4(1-17)Online publication date: 28-Jun-2018
          • (2016)Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingACM Transactions on Design Automation of Electronic Systems10.1145/285603121:3(1-22)Online publication date: 19-Apr-2016
          • (2015)Common-Centroid FinFET Placement Considering the Impact of Gate MisalignmentProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2717769(25-31)Online publication date: 29-Mar-2015

          View Options

          View options

          Media

          Figures

          Other

          Tables

          Share

          Share

          Share this Publication link

          Share on social media