More Web Proxy on the site http://driver.im/

research-article

Don't forget the I/O when allocating your LLC

Authors:

Mohammad Alian,

Nam Sung KimAuthors Info & Claims

ISCA '21: Proceedings of the 48th Annual International Symposium on Computer Architecture

Pages 112 - 125

https://doi.org/10.1109/ISCA52012.2021.00018

Published: 25 November 2021 Publication History

Abstract

In modern server CPUs, last-level cache (LLC) is a critical hardware resource that exerts significant influence on the performance of the workloads, and how to manage LLC is a key to the performance isolation and QoS in the cloud with multi-tenancy. In this paper, we argue that in addition to CPU cores, high-speed I/O is also important for LLC management. This is because of an Intel architectural innovation - Data Direct I/O (DDIO) - that directly injects the inbound I/O traffic to (part of) the LLC instead of the main memory. We summarize two problems caused by DDIO and show that (1) the default DDIO configuration may not always achieve optimal performance, (2) DDIO can decrease the performance of non-I/O workloads that share LLC with it by as high as 32%.

We then present IAT, the first LLC management mechanism that treats the I/O as the first-class citizen. IAT monitors and analyzes the performance of the core/LLC/DDIO using CPU's hardware performance counters and adaptively adjusts the number of LLC ways for DDIO or the tenants that demand more LLC capacity. In addition, IAT dynamically chooses the tenants that share its LLC resource with DDIO to minimize the performance interference by both the tenants and the I/O. Our experiments with multiple microbenchmarks and real-world applications demonstrate that with minimal overhead, IAT can effectively and stably reduce the performance degradation caused by DDIO.

References

[1]

M. Alian, Y. Yuan, J. Zhang, R. Wang, M. Jung, and N. S. Kim, "Data direct I/O characterization for future I/O system exploration," in Proceedings of the 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'20), Virtual Event, Aug. 2020.

Digital Library

[2]

S. Angel, H. Ballani, T. Karagiannis, G. O'Shea, and E. Thereska, "End-to-end performance isolation through virtual datacenters," in Proceedings of the 11st USENIX Symposium on Operating Systems Design and Implementation (OSDI'14), Broomfield, CO, Oct. 2014.

Digital Library

[3]

Ansyun Inc., "DPDK native accelerated network stack," https://www.ansyun.com, accessed in 2021.

[4]

D. Ardelean, A. Diwan, and C. Erdman, "Performance analysis of cloud applications," in Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI'18), Renton, WA, Apr. 2018.

Digital Library

[5]

arm, "Arm DynamIQ shared unit technical reference manual," https://developer.arm.com/documentation/100453/0300/functional-description/l3-cache/cache-stashing, accessed in 2021.

[6]

T. Barbette, C. Soldani, and L. Mathy, "Fast userspace packet processing," in Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '15), Oakland, CA, May 2015.

Digital Library

[7]

R. Bitirgen, E. Ipek, and J. F. Martinez, "Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach," in Proceedinsg of the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO'08), Lake Como, Italy, Nov. 2008.

Digital Library

[8]

S. Chen, C. Delimitrou, and J. F. Martínez, "PARTIES: QoS-aware resource partitioning for multiple interactive services," in Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'19), Providence, RI, Apr. 2019.

Digital Library

[9]

B. F. Cooper, A. Silberstein, E. Tam, R. Ramakrishnan, and R. Sears, "Benchmarking cloud serving systems with YCSB," in Proceedings of the 1st ACM Symposium on Cloud Computing (SoCC'10), Indianapolis, IN, Jun. 2010.

Digital Library

[10]

Y. Dong, X. Yang, J. Li, G. Liao, K. Tian, and H. Guan, "High performance network virtualization with SR-IOV," Journal of Parallel and Distributed Computing, vol. 72, no. 11, 2012.

Digital Library

[11]

N. El-Sayed, A. Mukkara, P.-A. Tsai, H. Kasture, X. Ma, and D. Sanchez, "KPart: A hybrid cache partitioning-sharing technique for commodity multicores," in Proceedings of the 24th IEEE International Symposium on High Performance Computer Architecture (HPCA'18), Vienna, Austria, Feb. 2018.

[12]

Facebook, "RocksDB: A persistent key-value store for fast storage environments," https://rocksdb.org, accessed in 2021.

[13]

A. Farshin, A. Roozbeh, G. Q. Maguire Jr., and D. Kostić, "Make the most out of last level cache in Intel processors," in Proceedings of the 14th European Conference on Computer Systems (EuroSys'19), Dresden, Germany, Mar. 2019.

Digital Library

[14]

A. Farshin, "Reexamining direct cache access to optimize I/O intensive applications for multi-hundred-gigabit networks," in Proceedings of 2020 USENIX Annual Technical Conference (ATC'20), Virtual Event, Jul. 2020.

Digital Library

[15]

D. Firestone, "VFP: A virtual switch platform for host SDN in the public cloud," in Proceedings of the 14th USENIX Symposium on Networked Systems Design and Implementation (NSDI'17), Boston, MA, Apr. 2017.

Digital Library

[16]

D. Firestone, A. Putnam, S. Mundkur, D. Chiou, A. Dabagh, M. Andrewartha, H. Angepat, V. Bhanu, A. Caulfield, E. Chung, H. K. Chandrappa, S. Chaturmohta, M. Humphrey, L. Jack, L. Norman, F. Liu, K. Ovtcharov, J. Padhye, G. Popuri, S. Raindel, T. Sapre, M. Shaw, M. Silva, Ganriel nd Sivakumar, N. Srivastava, A. Verma, Q. Zuhair, D. Bansal, D. Burger, K. Vaid, D. A. Maltz, and A. Greenberg, "Azure accelerated networking: SmartNICs in the public cloud," in Proceedings of the 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI'18), Renton, WA, Apr. 2018.

Digital Library

[17]

J. Fried, Z. Ruan, A. Ousterhout, and A. Belay, "Caladan: Mitigating interference at microsecond timescales," in Proceedigs of the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI'20), Virtual Event, Nov. 2020.

Digital Library

[18]

H. Golestani, A. Mirhosseini, and T. F. Wenisch, "Software data planes: You can't always spin to win," in Proceedings of the ACM Symposium on Cloud Computing (SoCC'19), Santa Cruz, CA, Nov. 2019.

Digital Library

[19]

M. Gottscho, S. Govindan, B. Sharma, M. Shoaib, and P. Gupta, "X-Mem: A cross-platform and extensible memory characterization tool for the cloud," in 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'16), Uppsala, Sweden, Jun. 2016.

[20]

J. Han, S. Jeon, Y.-r. Choi, and J. Huh, "Interference management for distributed parallel applications in consolidated clusters," in Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '16), Atlanta, GA, Apr. 2016.

Digital Library

[21]

J. L. Henning, "SPEC CPU2006 benchmark descriptions," ACM SIGARCH Computer Architecture News, vol. 34, no. 4, 2006.

Digital Library

[22]

A. Herdrich, E. Verplanke, P. Autee, R. Illikkal, C. Gianos, R. Singhal, and R. Iyer, "Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family," in Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA'16), Barcelona, Spain, Mar. 2016.

[23]

R. Huggahalli, R. Iyer, and S. Tetrick, "Direct cache access for high bandwidth network I/O," in Proceedings of the 32nd International Symposium on Computer Architecture (ISCA '05), Madison, WI, Jun. 2005.

Digital Library

[24]

J. Hwang, K. K. Ramakrishnan, and T. W. and, "NetVM: High performance and flexible networking using virtualization on commodity platforms," in Proceedings of 11th USENIX Symposium on Networked Systems Design and Implementation (NSDI'14), Seattle, WA, Apr. 2014.

Digital Library

[25]

Intel Corporation, "Data plane development kit (DPDK)," https://www.dpdk.org, accessed in 2021.

[26]

Intel Corporation, "Intel 64 and IA-32 architectures software developer's manual volume 4: Model-specific registers," https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-4-model-specific-registers, accessed in 2021.

[27]

Intel Corporation, "Intel Ethernet converged network adapter XL710 10/40 GbE," https://www.intel.com/content/www/us/en/ethernet-products/converged-network-adapters/ethernet-xl710-brief.html, accessed in 2021.

[28]

Intel Corporation, "Intel resource director technology (Intel RDT)," https://www.intel.com/content/www/us/en/architecture-and-technology/resource-director-technology.html, accessed in 2021.

[29]

Intel Corporation, "Intel Xeon Gold 6140 processor," https://ark.intel.com/content/www/us/en/ark/products/120485/intel-xeon-gold-6140-processor-24-75m-cache-2-30-ghz.html, accessed in 2021.

[30]

Intel Corporation, "Intel Xeon processor Scalable family uncore reference manual," https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-uncore-performance-monitoring-manual.html, accessed in 2021.

[31]

Intel Corporation, "Intel® data direct I/O (DDIO)," https://www.intel.com/content/www/us/en/io/data-direct-i-o-technology.html, accessed in 2021.

[32]

Intel Corporation, "User space software for Intel resource director technology," https://github.com/intel/intel-cmt-cat, accessed in 2021.

[33]

C. Iorgulescu, R. Azimi, Y. Kwon, S. Elnikety, M. Syamala, V. Narasayya, H. Herodotou, P. Tomita, A. Chen, J. Zhang, and J. Wang, "Perfiso: Performance isolation for commercial latency-sensitive services," in Proceedings of 2018 USENIX Annual Technical Conference (ATC'18), Boston, MA, Jul. 2018.

Digital Library

[34]

G. Irazoqui, T. Eisenbarth, and B. Sunar, "Systematic reverse engineering of cache slice selection in intel processors," in Proceedings of the 2015 Euromicro Conference on Digital System Design (DSD'15), Funchal, Madeira, Portugal, Aug. 2015.

Digital Library

[35]

A. Jaleel, "Memory characterization of workloads using instrumentation-driven simulation," Web Copy: http://www.jaleels.org/ajaleel/publications/SPECanalysis.pdf, 2010.

[36]

A. Kalia, D. Andersen, and M. Kaminsky, "Challenges and solutions for fast remote persistent memory access," in Proceedings of the 11th ACM Symposium on Cloud Computing (SoCC'20), Virtual Event, Oct. 2020.

Digital Library

[37]

M. Kambadur, T. Moseley, R. Hank, and M. A. Kim, "Measuring interference between live datacenter applications," in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC'12), Salt Lake City, UT, Nov. 2012.

Digital Library

[38]

G. Kappes and S. V. Anastasiadis, "A user-level toolkit for storage I/O isolation on multitenant hosts," in Proceedings of the 11th ACM Symposium on Cloud Computing (SoCC'20), Virtual Event, Oct. 2020.

Digital Library

[39]

H. Kasture and D. Sanchez, "Ubik: Efficient cache sharing with strict QoS for latency-critical workloads," in Proceedings of the 19th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'14), Salt Lake City, UT, Mar. 2014.

Digital Library

[40]

Keith Wiles, "Pktgen - traffic generator powered by DPDK," https://github.com/pktgen/Pktgen-DPDK, accessed in 2021.

[41]

C. Kim, D. Burger, and S. W. Keckler, "An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches," in Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'02), San Jose, CA, Oct. 2002.

Digital Library

[42]

N. Kulkarni, G. Gonzalez-Pumariega, A. Khurana, C. A. Shoemaker, C. Delimitrou, and D. H. Albonesi, "CuttleSys: Data-driven resource management for interactive services on reconfigurable multicores," in Proceedings of the 53rd IEEE/ACM International Symposium on Microarchitecture (MICRO'20), Virtual Event, Oct. 2020.

[43]

I. Kurakin and R. Khatko, "IO issues: Remote socket accesses," https://software.intel.com/en-us/vtune-cookbook-io-issues-remote-socket-accesses, accessed in 2021.

[44]

M. Kurth, B. Gras, D. Andriesse, C. Giuffrida, H. Bos, and K. Razavi, "NetCAT: Practical cache attacks from the network," in Proceedings of the 41st IEEE Symposium on Security and Privacy (Oakland'20), Virtual Event, May 2020.

[45]

D. Kwon, J. Boo, D. Kim, and J. Kim, "FVM: FPGA-assisted virtual device emulation for fast, scalable, and flexible storage virtualization," in Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI'20), Virtual Event, Nov. 2020.

Digital Library

[46]

Q. Llull, S. Fan, S. M. Zahedi, and B. C. Lee, "Cooper: Task colocation with cooperative games," in Proceedings of 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA'17), Austin, TX, Feb. 2017.

[47]

F. Manco, C. Lupu, F. Schmidt, J. Mendes, S. Kuenzer, S. Sati, K. Yasukata, C. Raiciu, and F. Huici, "My VM is lighter (and safer) than your container," in Proceedings of the 26th ACM Symposium on Operating Systems Principles (SOSP'17), Shanghai, China, Oct. 2017.

Digital Library

[48]

A. Manousis, R. A. Sharma, V. Sekar, and J. Sherry, "Contention-aware performance prediction for virtualized network functions," in Proceedings of the 2020 ACM SIGCOMM Conference (SIGCOMM'20), Virtual Event, Aug. 2020.

Digital Library

[49]

J. Mars, L. Tang, R. Hundt, K. Skadron, and M. L. Soffa, "Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations," in Proceedings of the 44th IEEE/ACM International Symposium on Microarchitecture (MICRO'11), Porto Alegre, Brazil, Dec. 2011.

Digital Library

[50]

M. Marty, M. de Kruijf, J. Adriaens, C. Alfeld, S. Bauer, C. Contavalli, M. Dalton, N. Dukkipati, W. C. Evans, S. Gribble, N. Kidd, R. Kononov, G. Kumar, C. Mauer, E. Musick, L. Olson, E. Rubow, M. Ryan, K. Springborn, P. Turner, V. Valancius, X. Wang, and A. Vahdat, "Snap: A microkernel approach to host networking," in Proceedings of the 27th ACM Symposium on Operating Systems Principles (SOSP'19), Huntsville, Canada, Oct. 2019.

Digital Library

[51]

C. Maurice, N. Scouarnec, C. Neumann, O. Heen, and A. Francillon, "Reverse engineering Intel last-level cache complex addressing using performance counters," in Proceedings of the 18th International Symposium on Research in Attacks, Intrusions, and Defenses (RAID'15), Kyoto, Japan, Nov. 2015.

Digital Library

[52]

NETRONOME, "Agilio OVS software," https://www.netronome.com/products/agilio-software/agilio-ovs-software/, accessed in 2021.

[53]

Network Working Group, "Benchmarking methodology for network interconnect devices," https://tools.ietf.org/html/rfc2544, accessed in 2021.

[54]

R. Neugebauer, G. Antichi, J. F. Zazo, Y. Audzevich, S. López-Buedo, and A. W. Moore, "Understanding PCIe performance for end host networking," in Proceedings of the 2018 ACM SIGCOMM Conference (SIGCOMM'18), Budapest, Hungary, Aug. 2018.

Digital Library

[55]

Nvidia, "Socket direct adapters," https://www.nvidia.com/en-us/networking/ethernet/socket-direct/, accessed in 2021.

[56]

A. Ousterhout, J. Fried, J. Behrens, A. Belay, and H. Balakrishnan, "Shenango: Achieving high CPU efficiency for latency-sensitive datacenter workloads," in Proceedings of the 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI'19), Boston, MA, Feb. 2019.

Digital Library

[57]

J. Park, S. Park, and W. Baek, "CoPart: Coordinated partitioning of last-level cache and memory bandwidth for fairness-aware workload consolidation on commodity servers," in Proceedings of the 14th European Conference on Computer Systems (EuroSys'19), Dresden, Germany, Mar. 2019.

Digital Library

[58]

T. Patel, R. Garg, and D. Tiwari, "GIFT: A coupon based throttle-and-reward mechanism for fair and efficient I/O bandwidth management on parallel storage systems," in Proceedings of the 18th USENIX Conference on File and Storage Technologies (FAST'20), Santa Clara, CA, Feb. 2020.

Digital Library

[59]

T. Patel and D. Tiwari, "CLITE: Efficient and QoS-aware co-location of multiple latency-critical jobs for warehouse scale computers," in Proceedings of 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA'20), San Diego, CA, Feb. 2020.

[60]

B. Pfaff, J. Pettit, T. Koponen, E. J. Jackson, A. Zhou, J. Rajahalme, J. Gross, A. Wang, J. Stringer, P. Shelar, K. Amidon, and M. Casado, "The design and implementation of Open vSwitch," in Proceedings of the 12th USENIX Symposium on Networked Systems Design and Implementation (NSDI'15), Okaland, CA, May 2015.

Digital Library

[61]

H. Qiu, S. S. Banerjee, S. Jha, Z. T. Kalbarczyk, and R. K. Iyer, "FIRM: An intelligent fine-grained resource management framework for SLO-oriented microservices," in Proceedings of 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI'20), Virtual Event, Nov. 2020.

Digital Library

[62]

M. K. Qureshi and Y. N. Patt, "Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches," in Proceedings of the 39th IEEE/ACM International Symposium on Microarchitecture (MICRO'06), Orlando, FL, Dec. 2006.

Digital Library

[63]

redislabs, "Redis," https://redis.io, accessed in 2021.

[64]

R. Russell, "Virtio: Towards a de-facto standard for virtual I/O devices," ACM SIGOPS Operating Systems Review, vol. 42, no. 5, Jul. 2008.

Digital Library

[65]

A. Sandberg, A. Sembrant, E. Hagersten, and D. Black-Schaffer, "Modeling performance variation due to cache sharing," in Proceedings of the 2013 IEEE International Symposium on High Performance Computer Architecture (HPCA'13), Shenzhen, China, Feb. 2013.

Digital Library

[66]

V. Selfa, J. Sahuquillo, L. Eeckhout, S. Petit, and M. E. Gómez, "Application clustering policies to address system fairness with Intel's cache allocation technology," in Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques (PACT'17), Portland, OR, Nov. 2017.

[67]

I. Smolyar, A. Markuze, B. Pismenny, H. Eran, G. Zellweger, A. Bolen, L. Liss, A. Morrison, and D. Tsafrir, "IOctopus: Outsmarting nonuniform DMA," in Proceedings of the 25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'20), Virtual Event, Mar. 2020.

Digital Library

[68]

M. Tirmazi, A. Barker, N. Deng, M. E. Haque, Z. G. Qin, S. Hand, M. Harchol-Balter, and J. Wilkes, "Borg: The next generation," in Proceedings of the Fifteenth European Conference on Computer Systems (EuroSys'20), Virtual Event, Apr. 2020.

Digital Library

[69]

A. Tootoonchian, A. Panda, C. Lan, M. Walls, K. Argyraki, S. Ratnasamy, and S. Shenker, "ResQ: Enabling SLOs in network function virtualization," in Proceedings of 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI'18), Renton, WA, Apr. 2018.

Digital Library

[70]

N. Vasić, D. Novaković, S. Miučin, D. Kostić, and R. Bianchini, "DejaVu: Accelerating resource allocation in virtualized environments," in Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'12), London, England, UK, Mar. 2012.

Digital Library

[71]

R. Wang and L. Chen, "Futility scaling: High-associativity cache partitioning," in Proceedings of the 47th IEEE/ACM International Symposium on Microarchitecture (MICRO'14), Cambridge, UK, Dec. 2014.

Digital Library

[72]

X. Wang, S. Chen, J. Setter, and J. F. Martínez, "SWAP: Effective fine-grain management of shared last-level caches with minimum hardware support," in Proceedings of 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA'17), Austin, TX, Feb. 2017.

[73]

Y. Xiang, X. Wang, Z. Huang, Z. Wang, Y. Luo, and Z. Wang, "DCAPS: Dynamic cache allocation with partial sharing," in Proceedings of the 13th European Conference on Computer Systems (EuroSys'18), Porto, Portugal, Apr. 2018.

Digital Library

[74]

C. Xu, K. Rajamani, A. Ferreira, W. Felter, J. Rubio, and Y. Li, "dCat: Dynamic cache management for efficient, performance-sensitive infrastructure-as-a-service," in Proceedings of the 13th European Conference on Computer Systems (EuroSys'18), Porto, Portugal, Apr. 2018.

Digital Library

[75]

Z. Yang, J. R. Harris, B. Walker, D. Verkamp, C. Liu, C. Chang, G. Cao, J. Stern, V. Verma, and L. E. Paul, "SPDK: A development kit to build high performance storage applications," in Proceedings of the 9th IEEE International Conference on Cloud Computing Technology and Science (CloudCom'17), Hong Kong, China, Dec. 2017.

[76]

Y. Ye, R. West, Z. Cheng, and Y. Li, "COLORIS: A dynamic cache partitioning system using page coloring," in Proceedings of the 23rd International Conference on Parallel Architecture and Compilation Techniques (PACT'14), Edmonton, Canada, Aug. 2014.

Digital Library

[77]

Y. Zhang, J. Chen, X. Jiang, Q. Liu, I. M. Steriner, A. J. Herdrich, K. Shu, R. Das, L. Cui, and L. Jiang, "LIBRA: Clearing the cloud through dynamic memory bandwidth management," in Proceedings of the 27th IEEE International Symposium on High-performance Computer Architecture (HPCA'21), Virtual Event, Feb. 2021.

[78]

H. Zhu and M. Erez, "Dirigent: Enforcing QoS for latency-critical tasks on shared multicore systems," in Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'16), Atlanta, GA, Apr. 2016.

Digital Library

Cited By

Dang YXia ZLi HSekar VYu MSeneviratne AVeitch D(2024)POSTER: Bring I-Cache to Light in Data Plane ApplicationsProceedings of the ACM SIGCOMM 2024 Conference: Posters and Demos10.1145/3672202.3673724(28-30)Online publication date: 4-Aug-2024
https://dl.acm.org/doi/10.1145/3672202.3673724
Schuh HKrishnamurthy ACuller DLevy HRizzo LKhan SStephens BTsafrir DMUSUVATHI MGupta RAbu-Ghazaleh N(2024)CC-NIC: a Cache-Coherent Interface to the NICProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624868(52-68)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3617232.3624868
Miano SSanaee ARisso FRétvári GAntichi G(2024)Morpheus: A Run Time Compiler and Optimizer for Software Data PlanesIEEE/ACM Transactions on Networking10.1109/TNET.2023.334628632:3(2269-2284)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1109/TNET.2023.3346286
Show More Cited By

Index Terms

Don't forget the I/O when allocating your LLC

Index terms have been assigned to the content through auto-classification.

Recommendations

Make the Most out of Last Level Cache in Intel Processors
EuroSys '19: Proceedings of the Fourteenth EuroSys Conference 2019

In modern (Intel) processors, Last Level Cache (LLC) is divided into multiple slices and an undocumented hashing algorithm (aka Complex Addressing) maps different parts of memory address space among these slices to increase the effective memory ...
Adaptive insertion policies for managing shared caches
PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques

Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, the conventional LRU replacement policy can significantly degrade cache ...
Sharer status-based caching in tiled multiprocessor systems-on-chip
HPC '15: Proceedings of the Symposium on High Performance Computing

In multi-core systems with cache-to-cache forwarding, the data access latency depends heavily on the sharer status of cache-lines (CLs). The sharer status of a CL is defined by the number of copies of the CL in the whole system. Exclusive single-copy ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '21: Proceedings of the 48th Annual International Symposium on Computer Architecture

June 2021

1168 pages

ISBN:9781450390866

General Chairs:
José Martínez
Cornell University
,
José Duato
Universitat Politècnica de València
,
Program Chair:
Lizy K. John
University of Texas at Austin

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

In-Cooperation

IEEE

Publisher

IEEE Press

Publication History

Published: 25 November 2021

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISCA '21

Sponsor:

SIGARCH

ISCA '21: The 48th Annual International Symposium on Computer Architecture

June 14 - 19, 2021

Virtual Event, Spain

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
186
Total Downloads

Downloads (Last 12 months)31
Downloads (Last 6 weeks)2

Reflects downloads up to 02 Mar 2025

Other Metrics

View Author Metrics

Citations

Cited By

Dang YXia ZLi HSekar VYu MSeneviratne AVeitch D(2024)POSTER: Bring I-Cache to Light in Data Plane ApplicationsProceedings of the ACM SIGCOMM 2024 Conference: Posters and Demos10.1145/3672202.3673724(28-30)Online publication date: 4-Aug-2024
https://dl.acm.org/doi/10.1145/3672202.3673724
Schuh HKrishnamurthy ACuller DLevy HRizzo LKhan SStephens BTsafrir DMUSUVATHI MGupta RAbu-Ghazaleh N(2024)CC-NIC: a Cache-Coherent Interface to the NICProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624868(52-68)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3617232.3624868
Miano SSanaee ARisso FRétvári GAntichi G(2024)Morpheus: A Run Time Compiler and Optimizer for Software Data PlanesIEEE/ACM Transactions on Networking10.1109/TNET.2023.334628632:3(2269-2284)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1109/TNET.2023.3346286
Sun YYuan YYu ZKuper RSong CHuang JJi HAgarwal SLou JJeong IWang RAhn JXu TKim N(2023)Demystifying CXL Memory with Genuine CXL-Ready Systems and DevicesProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614256(105-121)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614256
Jeong ILou JSon YPark YYuan YKim N(2023)LADIO: Leakage-Aware Direct I/O for I/O-Intensive WorkloadsIEEE Computer Architecture Letters10.1109/LCA.2023.329042722:2(77-80)Online publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1109/LCA.2023.3290427
Chatterjee BKhan SPande SKloeckner AMoreira J(2022)Com-CASProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569645(14-27)Online publication date: 8-Oct-2022
https://dl.acm.org/doi/10.1145/3559009.3569645
Wang MXu MWu J(2022)Understanding I/O Direct Cache Access Performance for End Host NetworkingACM SIGMETRICS Performance Evaluation Review10.1145/3547353.352266250:1(5-6)Online publication date: 7-Jul-2022
https://dl.acm.org/doi/10.1145/3547353.3522662
Wang MXu MWu J(2022)Understanding I/O Direct Cache Access Performance for End Host NetworkingProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/35080426:1(1-37)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3508042
Miano SSanaee ARisso FRétvári GAntichi GFalsafi BFerdman MLu SWenisch T(2022)Domain specific run time optimization for software data planesProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507769(1148-1164)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507769
Pismenny BLiss LMorrison ATsafrir DFalsafi BFerdman MLu SWenisch T(2022)The benefits of general-purpose on-NIC memoryProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507711(1130-1147)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507711
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten