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10.1109/FCCM.2015.63guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders

Published: 02 May 2015 Publication History

Abstract

Computing on field-programmable gate arrays (FPGAs) has been receiving continued interest as it provides high performance at relatively low power budgets, while avoiding the high non-recurring engineering (NRE) costs associated with ASIC designs. However, FPGA development is typically performed using register transfer level (RTL) languages which make the design process protracted and error-prone when compared to software design flows. To ease these problems, high-level synthesis (HLS) tools have been introduced which abstract away the RTL architecture description from the designer. In this work we explore the design space of a nonbinary GF (q) low-density parity-check (LDPC) decoder using Vivado HLS and compare it with state-of-the-art RTL designs.

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Published In

cover image Guide Proceedings
FCCM '15: Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines
May 2015
239 pages
ISBN:9781479999699

Publisher

IEEE Computer Society

United States

Publication History

Published: 02 May 2015

Author Tags

  1. Vivado
  2. design space exploration
  3. fast hardware design
  4. high-level synthesis
  5. non-binary LDPC codes

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