Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders
Abstract
Recommendations
Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019One of the advantages of High-Level Synthesis (HLS), also called C-based VLSI-design, over traditional RT-level VLSI design flows, is that multiple micro-architectures of unique area vs. performance can be automatically generated by setting different ...
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs
The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes ...
Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration
GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022Raising the level of VLSI design abstraction to the behavioral level allows to generate different micro-architectures from the same behavioral description by simply setting different synthesis options. These are typically synthesis directives in the ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Publisher
IEEE Computer Society
United States
Publication History
Author Tags
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0