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Accelerating machine-learning kernels in hadoop using FPGAs

Published: 04 May 2015 Publication History

Abstract

Big data applications share inherent characteristics that are fundamentally different from traditional desktop CPU, parallel and web service applications. They rely on deep machine learning and data mining applications. A recent trend for big data analytics is to provide heterogeneous architectures to allow support for hardware specialization to construct the right processing engine for analytics applications. However, these specialized heterogeneous architectures require extensive exploration of design aspects to find the optimal architecture in terms of performance and cost. This paper analyzes how offloading computational intensive kernels of machine learning algorithms to a heterogeneous CPU+FPGA platform enhances the performance. We use the latest Xilinx Zynq boards for implementation and result analysis. Furthermore, we perform a comprehensive analysis of communication and computation overheads such as data I/O movements, and calling several standard libraries that can not be offloaded to the accelerator to understand how the speedup of each application will contribute to its overall execution in an end-to-end Hadoop MapReduce environment.

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Y. Shan, B. Wang, J. Yan, Y. Wang, N. Xu, and H. Yang, "FPMR: Mapreduce framework on FPGA," in Proc Annual ACM/SIGDA Int Symp Field Programmable Gate Arrays, 2010, pp. 93--102.
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T. Honjo and K. Oikawa, "Hardware acceleration of hadoop mapreduce," in 2013 IEEE Int. Conf. Big Data, Oct 2013, pp. 118--124.
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Z. Lin and P. Chow, "Zcluster: A zynq-based hadoop cluster," in Int. Conf. Field-Programmable Technology (FPT), Dec 2013, pp. 450--453.
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Cited By

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  • (2018)Architectural considerations for FPGA acceleration of machine learning applications in MapReduceProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229639(89-96)Online publication date: 15-Jul-2018
  • (2017)Towards a scalable and energy-efficient resource manager for coupling cluster computing with distributed embedded computingCluster Computing10.1007/s10586-017-0936-y20:4(3707-3720)Online publication date: 1-Dec-2017
  • (2016)Heterogeneous chip multiprocessor architectures for big data applicationsProceedings of the ACM International Conference on Computing Frontiers10.1145/2903150.2908078(400-405)Online publication date: 16-May-2016
  1. Accelerating machine-learning kernels in hadoop using FPGAs

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    Published In

    cover image ACM Other conferences
    CCGRID '15: Proceedings of the 15th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing
    May 2015
    1277 pages
    ISBN:9781479980062

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    IEEE Press

    Publication History

    Published: 04 May 2015

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    Author Tags

    1. FPGA
    2. acceleration
    3. big data

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    • (2018)Architectural considerations for FPGA acceleration of machine learning applications in MapReduceProceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1145/3229631.3229639(89-96)Online publication date: 15-Jul-2018
    • (2017)Towards a scalable and energy-efficient resource manager for coupling cluster computing with distributed embedded computingCluster Computing10.1007/s10586-017-0936-y20:4(3707-3720)Online publication date: 1-Dec-2017
    • (2016)Heterogeneous chip multiprocessor architectures for big data applicationsProceedings of the ACM International Conference on Computing Frontiers10.1145/2903150.2908078(400-405)Online publication date: 16-May-2016

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