Article

Auto-adaptive reconfigurable architecture for scalable multimedia applications

Authors:

Xun ZHANG,

Hassan RABAH,

Serge WEBERAuthors Info & Claims

AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems

Pages 139 - 145

https://doi.org/10.1109/AHS.2007.34

Published: 05 August 2007 Publication History

Publisher Site

Abstract

The paper presents a layered reconfigurable architecture based on partial and dynamical reconfigurable FPGA in order to meet the adaptivity and scalability needs in multimedia applications. An efficient adaptivity is enabled thanks to the introduction of an application adaptive level and a task adaptive level organisation. This organisation is materialized through a global hardware reconfiguration and local hardware reconfiguration by using partial and dynamic reconfiguration of FPGAs. A case study of a discret wavelet transform is used to demonstrate the feasibility in task adaptive level considering different types of filters. A platform based on a Xilinx Virtex-4 FPGA is used for experimental implementation.

Cited By

View all

Pande AZambreno J(2012)Poly-DWTACM Transactions on Embedded Computing Systems10.1145/2146417.214642311:1(1-26)Online publication date: 5-Apr-2012
https://dl.acm.org/doi/10.1145/2146417.2146423
Otero AKrasteva Yde la Torre ERiesgo T(2010)Generic systolic array for run-time scalable coresProceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications10.1007/978-3-642-12133-3_4(4-16)Online publication date: 17-Mar-2010
https://dl.acm.org/doi/10.1007/978-3-642-12133-3_4

Index Terms

Auto-adaptive reconfigurable architecture for scalable multimedia applications
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors
2. Information systems
  1. Information systems applications
    1. Multimedia information systems

Recommendations

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as ...
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines

Recently, computer architectures that combine a reconfigurable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of fine grain parallelism in applications. ...
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

Field-programmable gate arrays (FPGAs) have become an extremely popular implementation technology for custom hardware because they offer a combination of low cost and very fast turnaround. Because of their in-system reconfigurability, FPGAs have also ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems

August 2007

736 pages

ISBN:076952866X

Publisher

IEEE Computer Society

United States

Publication History

Published: 05 August 2007

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 01 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Pande AZambreno J(2012)Poly-DWTACM Transactions on Embedded Computing Systems10.1145/2146417.214642311:1(1-26)Online publication date: 5-Apr-2012
https://dl.acm.org/doi/10.1145/2146417.2146423
Otero AKrasteva Yde la Torre ERiesgo T(2010)Generic systolic array for run-time scalable coresProceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications10.1007/978-3-642-12133-3_4(4-16)Online publication date: 17-Mar-2010
https://dl.acm.org/doi/10.1007/978-3-642-12133-3_4

Abstract

Cited By

Index Terms

Recommendations

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications

Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations