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Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Published: 03 May 2010 Publication History

Abstract

Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network-on-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the inter-router wires.

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  • (2018)Determining Effective Shortest Path in Asynchronous Network-on-Chip Through Bio-Inspired Optimization TechniquesWireless Personal Communications: An International Journal10.1007/s11277-018-5373-6102:4(3375-3392)Online publication date: 1-Oct-2018
  • (2017)Architecture level analysis for process variation in synchronous and asynchronous Networks-on-ChipJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.12.019102:C(175-185)Online publication date: 1-Apr-2017
  • (2016)Achieving lightweight multicast in asynchronous networks-on-chip using local speculationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897978(1-6)Online publication date: 5-Jun-2016
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  1. Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

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    Published In

    cover image Guide Proceedings
    NOCS '10: Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
    May 2010
    255 pages
    ISBN:9780769540535

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 03 May 2010

    Author Tags

    1. CAD
    2. EDA
    3. GALS
    4. NoC
    5. SoC
    6. asynchronous
    7. floorplan
    8. network
    9. router
    10. topology

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    View all
    • (2018)Determining Effective Shortest Path in Asynchronous Network-on-Chip Through Bio-Inspired Optimization TechniquesWireless Personal Communications: An International Journal10.1007/s11277-018-5373-6102:4(3375-3392)Online publication date: 1-Oct-2018
    • (2017)Architecture level analysis for process variation in synchronous and asynchronous Networks-on-ChipJournal of Parallel and Distributed Computing10.1016/j.jpdc.2016.12.019102:C(175-185)Online publication date: 1-Apr-2017
    • (2016)Achieving lightweight multicast in asynchronous networks-on-chip using local speculationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897978(1-6)Online publication date: 5-Jun-2016
    • (2013)Low-power networks-on-chipProceedings of the 2013 International Symposium on Low Power Electronics and Design10.5555/2648668.2648700(132-134)Online publication date: 4-Sep-2013
    • (2013)A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systemsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485370(332-337)Online publication date: 18-Mar-2013
    • (2011)Link pipelining strategies for an application-specific asynchronous NoCProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999976(185-192)Online publication date: 1-May-2011

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