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research-article

Co-Design and System for the Supercomputer “Fugaku”

Published: 01 March 2022 Publication History

Abstract

The supercomputer “Fugaku” is an exascale manycore-based parallel system developed as a Japanese national flagship supercomputer in the FLAGSHIP 2020 Project. While “Fugaku” was ranked first for several benchmarks such as TOP500, HPCG, HPL-AI, and Graph500 in 2020, the major design concept is the application-first concept by the co-design for power efficiency and high performance. We have designed an original manycore processor based on Armv8 instruction sets with the scalable vector extension, A64FX processor, with Fujitsu, our industry partner. The system consists of 158,976 nodes with 7.6 million cores in total and a theoretical peak of 537 Peta Floating-point Operations Per Second in double-precision floating points, connected by Tofu-D interconnect. The high performance computing (HPC)-oriented design enables an extremely good performance for memory-intensive workloads thanks to HBM2 memory with breakthrough power efficiency. In this article, we present the pragmatic practice of our co-design effort for “Fugaku” followed by an overview and the performance of “Fugaku.”

References

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Cited By

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  • (2024)Optimizing Attention by Exploiting Data Reuse on ARM Multi-core CPUsProceedings of the 38th ACM International Conference on Supercomputing10.1145/3650200.3656620(137-149)Online publication date: 30-May-2024
  • (2024)Analysis Towards Energy-Aware Image-based In Situ Visualization on the FugakuProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3635035.3635048(154-163)Online publication date: 18-Jan-2024
  • (2024)UNR: Unified Notifiable RMA Library for HPCProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00111(1-15)Online publication date: 17-Nov-2024
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Published In

cover image IEEE Micro
IEEE Micro  Volume 42, Issue 2
March-April 2022
84 pages

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 2022

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View all
  • (2024)Optimizing Attention by Exploiting Data Reuse on ARM Multi-core CPUsProceedings of the 38th ACM International Conference on Supercomputing10.1145/3650200.3656620(137-149)Online publication date: 30-May-2024
  • (2024)Analysis Towards Energy-Aware Image-based In Situ Visualization on the FugakuProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3635035.3635048(154-163)Online publication date: 18-Jan-2024
  • (2024)UNR: Unified Notifiable RMA Library for HPCProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00111(1-15)Online publication date: 17-Nov-2024
  • (2024)Exploring GPU-to-GPU Communication: Insights into Supercomputer InterconnectsProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00039(1-15)Online publication date: 17-Nov-2024
  • (2024)Scalable I/O aggregation for asynchronous multi-level checkpointingFuture Generation Computer Systems10.1016/j.future.2024.06.003160:C(420-432)Online publication date: 1-Nov-2024
  • (2023)Modelling Data Locality of Sparse Matrix-Vector Multiplication on the A64FXProceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624198(1334-1342)Online publication date: 12-Nov-2023
  • (2023)COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-CoresArchitecture of Computing Systems10.1007/978-3-031-42785-5_8(105-119)Online publication date: 13-Jun-2023
  • (2023)Evaluation of HPC Workloads Running on Open-Source RISC-V HardwareHigh Performance Computing10.1007/978-3-031-40843-4_40(538-551)Online publication date: 21-May-2023

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