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research-article

Fat Caches for Scale-Out Servers

Published: 01 March 2017 Publication History

Abstract

Emerging scale-out servers are characterized by massive memory footprints and bandwidth requirements. On-chip stacked DRAM caches have been proposed to provide the required bandwidth for manycore servers through caching of secondary data working sets. However, the disparity between provided capacity and working set sizes precludes their effective deployment in servers, calling for high-capacity cache architectures. High-capacity caches--enabled by the emergence of high-bandwidth memory technologies--exhibit high spatiotemporal locality due to coarse-grained access patterns and long cache residency periods stemming from skewed dataset access distributions. The observed spatiotemporal behavior favors a page-based organization that naturally exploits spatial locality while minimizing tag storage requirements and enabling a practical in-SRAM tag array architecture. By storing tags in SRAM, caches avoid the complexity of in-DRAM metadata found in state-of-the-art DRAM caches.

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  • (2024)sIOPMP: Scalable and Efficient I/O Protection for TEEsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640378(1061-1076)Online publication date: 27-Apr-2024
  • (2024)COAXIAL: A CXL-Centric Memory System for Scalable ServersProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00101(1-15)Online publication date: 17-Nov-2024
  • (2021)A complete robust control network based on skewed temporal logicJournal of High Speed Networks10.3233/JHS-21066627:3(265-278)Online publication date: 1-Jan-2021
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  1. Fat Caches for Scale-Out Servers

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    Published In

    cover image IEEE Micro
    IEEE Micro  Volume 37, Issue 2
    March 2017
    102 pages

    Publisher

    IEEE Computer Society Press

    Washington, DC, United States

    Publication History

    Published: 01 March 2017

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    • (2024)sIOPMP: Scalable and Efficient I/O Protection for TEEsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640378(1061-1076)Online publication date: 27-Apr-2024
    • (2024)COAXIAL: A CXL-Centric Memory System for Scalable ServersProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00101(1-15)Online publication date: 17-Nov-2024
    • (2021)A complete robust control network based on skewed temporal logicJournal of High Speed Networks10.3233/JHS-21066627:3(265-278)Online publication date: 1-Jan-2021
    • (2021)Rebooting virtual memory with midgardProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00047(512-525)Online publication date: 14-Jun-2021
    • (2020)Autonomous warehouse-scale computersProceedings of the 57th ACM/EDAC/IEEE Design Automation Conference10.5555/3437539.3437714(1-6)Online publication date: 20-Jul-2020
    • (2019)Morphable DRAM Cache Design for Hybrid Memory SystemsACM Transactions on Architecture and Code Optimization10.1145/333850516:3(1-24)Online publication date: 18-Jul-2019
    • (2019)Energy minimization in the STT-RAM-based high-capacity last-level cachesThe Journal of Supercomputing10.1007/s11227-019-02918-275:10(6831-6854)Online publication date: 1-Oct-2019
    • (2018)Algorithm/Architecture Co-Design for Near-Memory ProcessingACM SIGOPS Operating Systems Review10.1145/3273982.327399252:1(109-122)Online publication date: 28-Aug-2018
    • (2018)Design guidelines for high-performance SCM hierarchiesProceedings of the International Symposium on Memory Systems10.1145/3240302.3240310(3-16)Online publication date: 1-Oct-2018
    • (2018)Scale-out ccNUMAProceedings of the Thirteenth EuroSys Conference10.1145/3190508.3190550(1-15)Online publication date: 23-Apr-2018
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