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The Movidius Myriad Architecture's Potential for Scientific Computing

Published: 01 January 2015 Publication History

Abstract

In recent years, a new generation of ultralow-power processors have emerged that are aimed primarily at signal processing in mobile computing. However, their architecture could make some of these useful for other applications. Algorithms originally developed for scientific computing are used increasingly in signal conditioning and emerging fields such as computer vision, increasing the demand for computing power in mobile systems. In this article, the authors describe the design and implementation of dense matrix multiplication on the Movidius Myriad architecture and evaluate its performance and energy efficiency. The authors demonstrate a performance of 8.11 Gflops on the Myriad I processor and a performance/watt ratio of 23.17 Gflops/W for a key computational kernel. These results show significant potential for scientific-computing tasks and invite further research.

References

[1]
M. Ali etal., “Level-3 BLAS on the TI C6678 Multi-Core DSP,” Proc. IEEE 24th Int'l Symp. Computer Architecture and High Performance Computing, 2012, pp. 179–186.
[2]
S. Williams etal., “The Potential of the Cell Processor for Scientific Computing,” Proc. 3rd Conf. Computing Frontiers, 2006, pp. 9–20.
[3]
D. Moloney etal., “1TOPS/W Software Programmable Media Processor,” Hot Chips 23, 2011; www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.8-Video/HC23.19.811-1TOPS-Media-Moloney-Movidius.pdf.
[4]
J.J. Dongarra etal., “A Set of Level 3 Basic Linear Algebra Subprograms,” ACM Trans. Mathematical Software, vol. 16, no. 1, 1990, pp. 1–17.
[5]
D.C. Snowdon, S. Ruocco, and G. Heiser, “Power Management and Dynamic Voltage Scaling: Myths and Facts,” Proc. Workshop Power Aware Real-Time Computing, 2005; www.ssrg.nicta.com.au/publications/papers/Snowdon_RH_05.abstract.pml.
[6]
A. Miyoshi etal., “Critical Power Slope: Understanding the Runtime Effects of Frequency Scaling,” Proc. 16th Int'l Conf. Supercomputing (ICS 02), 2002, pp. 35–44.
[7]
B.R. Rau and C.D. Glaeser, “Some Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computing,” Proc. 14th Ann. Workshop Microprogramming (MICRO 14), 1981, pp. 183–198.
[8]
I. Kodukula etal., “An Experimental Evaluation of Tiling and Shackling for Memory Hierarchy Management,” Proc. 13th Int'l Conf. Supercomputing (ICS 99), 1999, pp. 482–491.
[9]
F.D. Igual etal., “Unleashing the High-Performance and Low-Power of Multi-core DSPs for General-Purpose HPC,” Proc. Int'l Conf. High Performance Computing, Networking, Storage and Analysis (SC 12), 2012, pp. 26:1–26:11.
[10]
A. Pedram, R. van de Geijn, and A. Gerstlauer, “Codesign Tradeoffs for High-Performance, Low Power Linear Algebra Architectures,” IEEE Trans. Computers, vol. 61, no. 12, 2012, pp. 1724–1736.
[11]
Intel Xeon Phi Product Family: Performance Brief, Intel, Dec. 2013; www.intel.com/content/www/us/en/benchmarks/xeon-phi-product-family-performance-brief.html.
[12]
S. Oberlin, Accelerating Exascale: How the End of Moore's Law Scaling is Changing the Machines You Use, the Way You Code, and the Algorithms You Use, Nvidia, Mar. 2014; www.siam.org/meetings/ex14/02-oberlin-slides.pdf.

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        cover image IEEE Micro
        IEEE Micro  Volume 35, Issue 1
        Jan.-Feb. 2015
        60 pages

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        IEEE Computer Society Press

        Washington, DC, United States

        Publication History

        Published: 01 January 2015

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        • (2023)Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUsACM Transactions on Design Automation of Electronic Systems10.1145/361789329:1(1-22)Online publication date: 20-Sep-2023
        • (2021)A Survey on Edge Performance BenchmarkingACM Computing Surveys10.1145/344469254:3(1-33)Online publication date: 22-Apr-2021
        • (2021)NNStreamerProceedings of the 43rd International Conference on Software Engineering: Software Engineering in Practice10.1109/ICSE-SEIP52600.2021.00029(198-207)Online publication date: 25-May-2021
        • (2019)A Neural Network Prefetcher for Arbitrary Memory Access PatternsACM Transactions on Architecture and Code Optimization10.1145/334500016:4(1-27)Online publication date: 15-Oct-2019

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