research-article

Virtualized ECC: Flexible Reliability in Main Memory

Authors:

Doe Hyun Yoon,

Mattan ErezAuthors Info & Claims

IEEE Micro, Volume 31, Issue 1

Pages 11 - 19

https://doi.org/10.1109/MM.2010.103

Published: 01 January 2011 Publication History

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Abstract

Virtualized error checking and correcting (ECC) is a scheme that virtualizes memory-error correction. Unlike traditional uniform ECC, which provides a fixed level of error tolerance, virtualized ECC enables flexible memory protection by mapping redundant information needed for correcting errors onto the memory namespace. Additionally, virtualized ECC enables error-correction mechanisms that can adapt to user and system demands.

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Shah DXue ZPattabiraman KAamodt T(2023)Characterizing and Improving Resilience of Accelerators to Memory Errors in Autonomous RobotsACM Transactions on Cyber-Physical Systems10.1145/36278288:3(1-33)Online publication date: 23-Oct-2023
https://dl.acm.org/doi/10.1145/3627828
Wang HZhao KLv MZhang XSun HZhang T(2017)Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error CorrectionIEEE Transactions on Computers10.1109/TC.2016.262175866:5(820-833)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2621758
Arslan STopcuoglu HKandemir MTosun O(2017)A selective protection scheme of applications using asymmetrically reliable cachesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00475:C(133-144)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.004
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Virtualized and flexible ECC for main memory
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Published In

IEEE Micro Volume 31, Issue 1

January 2011

126 pages

ISSN:0272-1732

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 January 2011

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Shah DXue ZPattabiraman KAamodt T(2023)Characterizing and Improving Resilience of Accelerators to Memory Errors in Autonomous RobotsACM Transactions on Cyber-Physical Systems10.1145/36278288:3(1-33)Online publication date: 23-Oct-2023
https://dl.acm.org/doi/10.1145/3627828
Wang HZhao KLv MZhang XSun HZhang T(2017)Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error CorrectionIEEE Transactions on Computers10.1109/TC.2016.262175866:5(820-833)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TC.2016.2621758
Arslan STopcuoglu HKandemir MTosun O(2017)A selective protection scheme of applications using asymmetrically reliable cachesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2016.12.00475:C(133-144)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1016/j.sysarc.2016.12.004
Chen HWu CMudge TChakrabarti C(2016)RATT-ECCACM Transactions on Architecture and Code Optimization10.1145/295775813:3(1-24)Online publication date: 17-Sep-2016
https://dl.acm.org/doi/10.1145/2957758
Arslan STopcuoglu HKandemir MTosun O(2016)Asymmetrically reliable caches for multicore architectures under performance and energy constraintsCluster Computing10.1007/s10586-016-0641-219:4(1819-1833)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10586-016-0641-2
Chen HArunkumar AWu CMudge TChakrabarti C(2015)E-ECCProceedings of the 2015 International Symposium on Memory Systems10.1145/2818950.2818961(60-70)Online publication date: 5-Oct-2015
https://dl.acm.org/doi/10.1145/2818950.2818961
Son YSeongil ORo YLee JAhn J(2013)Reducing memory access latency with asymmetric DRAM bank organizationsACM SIGARCH Computer Architecture News10.1145/2508148.248595541:3(380-391)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485955
Jian XDuwe HSartori JSridharan VKumar RGropp WMatsuoka S(2013)Low-power, low-storage-overhead chipkill correct via multi-line error correctionProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.1145/2503210.2503243(1-12)Online publication date: 17-Nov-2013
https://dl.acm.org/doi/10.1145/2503210.2503243
Giridhar BCieslak MDuggal DDreslinski RChen HPatti RHold BChakrabarti CMudge TBlaauw DGropp WMatsuoka S(2013)Exploring DRAM organizations for energy-efficient and resilient exascale memoriesProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.1145/2503210.2503215(1-12)Online publication date: 17-Nov-2013
https://dl.acm.org/doi/10.1145/2503210.2503215
Son YSeongil ORo YLee JAhn JMendelson A(2013)Reducing memory access latency with asymmetric DRAM bank organizationsProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485955(380-391)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485955

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Virtualized and flexible ECC for main memory

IVEC: off-chip memory integrity protection for both security and reliability

Virtualized and flexible ECC for main memory

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