A Survey of Microprocessor Architectures for Memory Management

Reviewer: Andrew Robert Huber

The virtual memory management facilities provided by six popular lines of microprocessors are reviewed in this survey. It covers the Intel 8086 series, including the 80286 and 80386 and the 432; the Motorola 68000 series; the National 16032 and 32032; the Zilog Z800 and Z8000 series; the AT&T WE32100; and the NCR/32. Issues discussed include segmentation versus paging, the use of associative caches for address translation, on-chip versus off-chip memory hardware, multilevel mapping techniques, instruction restart versus instruction continuation, and protection and security. That is too much ground to cover completely, and much of the coverage is necessarily skimpy. It would have been better to omit some topics; for example, the three pages devoted to protection are too inadequate to provide useful information. Part of the problem is that much of the material is excessively tutorial in nature, leaving little chance to explain adequately and to compare critically the various architectures. There are other weaknesses in the presentation, including the lack of a consistent terminology, awkward English (which the editors should have caught), and typographical and other errors (including an incorrect figure that indicates that microinstruction continuation after a fault is identical to microinstruction restart). The survey would also be much more valuable and timely if some RISC processors were included. (One of 36 references is from 1985; the rest are from 1984 or earlier.) The value of this survey is that it collects information on many microprocessor memory architectures in one place.