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Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design

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Masanori HashimotoAuthors Info & Claims

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Volume E89-A, Issue 12

Pages 3560 - 3568

https://doi.org/10.1093/ietfec/e89-a.12.3560

Published: 01 December 2006 Publication History

Abstract

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
1. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis

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cover image IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume E89-A, Issue 12

December 2006

362 pages

ISSN:0916-8508

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Oxford University Press, Inc.

United States

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Published: 01 December 2006

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Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

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