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On robust strong‐non‐interferent low‐latency multiplications

Authors:

Maria Chiara Molteni,

Jürgen Pulkus,

Vittorio ZaccariaAuthors Info & Claims

IET Information Security, Volume 16, Issue 2

Pages 127 - 132

https://doi.org/10.1049/ise2.12048

Published: 24 November 2021 Publication History

Abstract

The overarching goal of this work is to present new theoretical and practical tools to implement robust−t−probing security. In this work, a low‐latency multiplication gadget that is secure against probing attacks that exploit logic glitches in the circuit is presented. The gadget is the first of its kind to present a 1‐cycle input‐to‐output latency while belonging to the class of probing security by optimized composition gadgets [6]. In particular, the authors show that it is possible to construct robust‐t‐strong‐non‐interferent gadgets without compromising on latency with a moderate increase in area. The authors provide a theoretical proof for the robustness of the gadget and show that, for t≤4, the amount of randomness required can even be reduced without compromising on robustness.

References

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Cited By

Knichel DMoradi AYin HStavrou ACremers CShi E(2022)Low-Latency Hardware Private CircuitsProceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security10.1145/3548606.3559362(1799-1812)Online publication date: 7-Nov-2022
https://dl.acm.org/doi/10.1145/3548606.3559362

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Information

Published In

cover image IET Information Security

IET Information Security Volume 16, Issue 2

March 2022

69 pages

EISSN:1751-8717

DOI:10.1049/ise2.v16.2

Issue’s Table of Contents

© 2021 The Authors. IET Information Security published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.

This is an open access article under the terms of the Creative Commons Attribution‐NonCommercial‐NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non‐commercial and no modifications or adaptations are made.

Publisher

John Wiley & Sons, Inc.

United States

Publication History

Published: 24 November 2021

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Cited By

Knichel DMoradi AYin HStavrou ACremers CShi E(2022)Low-Latency Hardware Private CircuitsProceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security10.1145/3548606.3559362(1799-1812)Online publication date: 7-Nov-2022
https://dl.acm.org/doi/10.1145/3548606.3559362

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