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research-article

Ultra8T: : A sub-threshold 8T SRAM with leakage detection

Authors:

Yongliang Zhou,

Wenjian YuAuthors Info & Claims

Volume 98, Issue C

https://doi.org/10.1016/j.vlsi.2024.102233

Published: 18 October 2024 Publication History

Abstract

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing the sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (V D D M I N). In this work, we first propose a model that describes a specific relationship between read current and leakage noise in a given column. Based on the model, Ultra8T SRAM is designed to aggressively reduce V D D M I N by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256 × 64 array in 28 nm CMOS technology. Post-simulation results show successful read operation at 0.25 V with 1.11 μs read delay, and the minimum energy required is 1.69 pJ at 0.4 V

Highlights

•

Development of an 8T SRAM with leakage detection for sub-threshold operation at 0.25V.

•

Presenting a model to describe the relationship between read and leakage current.

•

Implementation of a digitized timing module for accurate read tracking and PVT handling.

References

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Index Terms

Ultra8T: A sub-threshold 8T SRAM with leakage detection
1. Hardware

Index terms have been assigned to the content through auto-classification.

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Information & Contributors

Information

Published In

cover image Integration, the VLSI Journal

Integration, the VLSI Journal Volume 98, Issue C

Sep 2024

226 pages

Issue’s Table of Contents

Elsevier B.V.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 18 October 2024

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