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Facilitating the design of fault tolerance in transaction level SystemC programs

Authors:

Reza Hajisheykhi,

Sandeep S. KulkarniAuthors Info & Claims

Theoretical Computer Science, Volume 496

Pages 50 - 68

https://doi.org/10.1016/j.tcs.2012.11.010

Published: 01 July 2013 Publication History

Abstract

Due to their increasing complexity, today's SoC (system on chip) systems are subject to a variety of faults (e.g., single-event upset, component crash, etc.), thereby making fault tolerance a highly important property of such systems. However, designing fault tolerance is a complex task in part due to the large scale of integration of SoC systems and different levels of abstraction provided by modern system design languages such as SystemC. Most existing methods enable fault injection and impact analysis as a means for increasing design dependability. Nonetheless, such methods provide little support for designing fault tolerance. To facilitate the design of fault tolerance in SoC systems, this paper proposes an approach for designing fault-tolerant inter-component communication protocols in SystemC transaction level modeling (TLM) programs. The proposed method includes four main steps, namely model extraction, fault modeling, addition of fault tolerance and refinement of fault tolerance to SystemC code. We demonstrate the proposed approach using a simple SystemC transaction level program that is subject to communication faults. Moreover, we illustrate how fault tolerance can be added to SystemC programs that use the base protocol of the TLM interoperability layer. We also illustrate how fault tolerance functionalities can be partitioned to software and hardware components. Finally, we put forward a roadmap for future research at the intersection of fault tolerance and hardware-software co-design.

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Cited By

Silva AParra PPolo ÓSánchez S(2014)Runtime instrumentation of SystemC/TLM2 interfaces for fault tolerance requirements verification in software cosimulationModelling and Simulation in Engineering10.1155/2014/1050512014(42-42)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1155/2014/105051
Hajisheykhi REbnenasir AKulkarni S(2013)Modeling and Analyzing Timing Faults in Transaction Level SystemC Programs15th International Symposium on Stabilization, Safety, and Security of Distributed Systems - Volume 825510.5555/2718693.2718718(344-347)Online publication date: 13-Nov-2013
https://dl.acm.org/doi/10.5555/2718693.2718718
Hajisheykhi REbnenasir AKulkarni SPalesi MMak TDaneshtalab M(2013)Modeling and analyzing timing faults in transaction level SystemC programsProceedings of the Sixth International Workshop on Network on Chip Architectures10.1145/2536522.2536533(65-68)Online publication date: 8-Dec-2013
https://dl.acm.org/doi/10.1145/2536522.2536533

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Published In

cover image Theoretical Computer Science

Theoretical Computer Science Volume 496, Issue

July, 2013

149 pages

ISSN:0304-3975

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Copyright © Elsevier B.V. © 2012.

Publisher

Elsevier Science Publishers Ltd.

United Kingdom

Publication History

Published: 01 July 2013

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Cited By

Silva AParra PPolo ÓSánchez S(2014)Runtime instrumentation of SystemC/TLM2 interfaces for fault tolerance requirements verification in software cosimulationModelling and Simulation in Engineering10.1155/2014/1050512014(42-42)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1155/2014/105051
Hajisheykhi REbnenasir AKulkarni S(2013)Modeling and Analyzing Timing Faults in Transaction Level SystemC Programs15th International Symposium on Stabilization, Safety, and Security of Distributed Systems - Volume 825510.5555/2718693.2718718(344-347)Online publication date: 13-Nov-2013
https://dl.acm.org/doi/10.5555/2718693.2718718
Hajisheykhi REbnenasir AKulkarni SPalesi MMak TDaneshtalab M(2013)Modeling and analyzing timing faults in transaction level SystemC programsProceedings of the Sixth International Workshop on Network on Chip Architectures10.1145/2536522.2536533(65-68)Online publication date: 8-Dec-2013
https://dl.acm.org/doi/10.1145/2536522.2536533

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