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CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques

Published: 01 October 2010 Publication History

Abstract

For implementing a dynamic binary translation system, traditional software-based solutions suffer from significant runtime overhead and are not suitable for extra complex optimization. This paper proposes using hardware-software collaboration techniques to create an high efficient dynamic binary translation system, CoDBT, which emulates several heterogeneous ISAs (Instruction Set Architectures) on a host processor without changing to the existing processor. We analyze the major performance bottlenecks via evaluating overhead of a pure software-solution DBT. Guidelines are provided for applying a suitable hardware-software partition process to CoDBT, as are algorithms for designing hardware-based binary translator and code cache management. An intermediate instruction set is introduced to make multi-source translation more practicable and scalable. Meantime, a novel runtime profiling strategy is integrated into the infrastructure to collect program hot spots information to supporting potential future optimizations. The advantages of using co-design as an implementation approach for DBT system are assessed by several SPEC benchmarks. Our results demonstrate that significant performance improvements can be achieved with appropriate hardware support choices. CoDBT could be an efficient and cost-effective solution for situations where the usual methods of performance acceleration for dynamic binary translation are inappropriate.

References

[1]
Baraz, L., Devor, T., Etzion, O., Goldenberg, S., Skaletsky, A., Wang, Y. and Zemach, Y., IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. IEEE Micro. 191-204.
[2]
K. Adams, O. Agesen, A comparison of software and hardware techniques for x86 virtualization, in: Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2006, pp. 2-13.
[3]
A.C. Klaiber, The technology behind Crusoe processors, Transmeta Technical Brief, 2000.
[4]
V. Bala, E. Duesterwald, S. Banerjia, Dynamo: a transparent dynamic optimization system, in: Proceedings of the International Conference on Programming Language Design and Implementation (PLDI), 2000, pp. 1-12.
[5]
E. Borin, C. Wang, Y. Wu, G. Araujo, Software-based transparent and comprehensive control-flow error detection, in: Proceedings of the International Conference on Code Generation and Optimization (CGO), 2006, pp. 333-345.
[6]
Coronato, A., Pietro, G.D. and Gallo, L., An agent based platform for task distribution in virtual environments. Journal of Systems Architecture: Embedded Systems Design. v54 i9. 877-882.
[7]
Kenneth B. Kent, Micaela Serra, R. Nigel Horspool, Hardware/software co-design for virtual machines, in: IEE Proceedings Computers and Digital Techniques, vol. 152 (5), September 2005, pp. 537-548.
[8]
F. Qin, C. Wang, Z. Li, H. Kim, Y. Zhou, Y. Wu, LIFT: a low-overhead practical information flow tracking system for detecting security attacks, in: Proceedings of the International Symposium on Microarchitecture (MICRO), 2006, pp. 135-148.
[9]
Q. Wu, M. Martonosi, D.W. Clark, V.J. Reddi, D. Connors, Y. Wu, J. Lee, D. Brooks, A dynamic compilation framework for controlling microprocessor energy and performance, in: Proceedings of the International Symposium on Microarchitecture (MICRO), 2005, pp. 271-282.
[10]
Halfhill, T.R., How to soup up Java (Part I). BYTE. v23 i5. 60-74.
[11]
Wayner, P., How to soup up Java (Part II): Nine recipes for fast easy, Java. BYTE. v23 i5. 76-80.
[12]
R. Radhakrishnan, R. Bhargava, L.K. John, Improving Java performance using hardware translation, in: Proceedings of the International Conference on Supercomputing (ICS), 2001, pp. 427-439.
[13]
Thomas, B. and James, L., Optimally profiling and tracing programs. ACM Transactions on Programming Languages and Systems. v16 i3. 1319-1360.
[14]
J.C. Dehnert, B. Grant, J.P. Banning, R. Johnson, T. Kistler, A. Klaiber, J. Mattson, The transmeta code morphing-software: using speculation, recovery, and adaptive retranslation to address real-life challenges, in: Proceedings of the International Conference on Code Generation and Optimization (CGO), 2003, pp. 15-24.
[15]
H. Kim, J.E. Smith, Hardware support for control transfers in code caches, in: Proceedings of the International Symposium on Microarchitecture (MICRO), 2003, pp. 253-264.
[16]
C. Wang, S. Hu, H. Kim, S.R. Nair, M. Breternitz, Z. Ying, Y. Wu, StarDBT: an efficient multi-platform dynamic binary translation system, in: Proceedings of the Asia-Pacific Computer Systems Architecture Conference, 2007, pp. 4-15.
[17]
F. Bellard, QEMU: a fast and portable dynamic translator, in: Proceedings of the USENIX Annual Technical Conference (USENIX), 2005, pp. 41-46.
[18]
Chernoff, A., Herdeg, M., Hookway, R., Reeve, C., Rubin, N., Tye, T., Yadavalli, S.B. and Yates, J., FX!32: a profile-directed binary translator. IEEE Micro. v18 i2. 56-64.
[19]
K. Scott, N. Kumar, S. Velusamy, B. Childers, J.W. Davidson, M.L. Soffa, Retargetable and reconfigurable software dynamic translation, in: Proceedings of the First International Symposium on Code Generation and Optimization, 2003, pp. 36-47.
[20]
Ung, D. and Cifuentes, C., Dynamic binary translation using run-time feedbacks. Journal of Science and Computer Programming(JSCP). v60 i2. 189-204.
[21]
Libby, J.C. and Kent, K.B., An embedded implementation of the Common Language Infrastructure. Journal of Systems Architecture: Embedded Systems Design. v55 i2. 114-126.
[22]
Wu, Y. and Lee, Y., Hardware-software collaborative techniques for runtime profiling and phase transition detection. Journal of Computer Science and Technology. v20 i5. 665-675.
[23]
Astarloa, A., Zuloaga, A., Bidarte, U., Martn, J.L., Lzaro, J. and Jimenez, J., Tornado: a self-reconfiguration control system for core-based multiprocessor CSoPCs. Journal of Systems Architecture. v53 i9. 629-643.
[24]
IBM, CoreConnect Bus Architecture, 1999. <http://www.chips.ibm.com/products/coreconnect>.
[25]
C. Cifuentes, B. Lewis, D. Ung, Walkabout: a retargetable dynamic binary translation framework, Sun Microsystems Technical Report 2002-106, Sun Microsystems Laboratories, 2002.

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  • (2019)Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translatorJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2019.07.00898:C(173-190)Online publication date: 1-Sep-2019
  • (2014)SPTUProceedings of International Conference on Systems and Storage10.1145/2611354.2611368(1-12)Online publication date: 30-Jun-2014
  • (2014)DTTProceedings of the 11th ACM Conference on Computing Frontiers10.1145/2597917.2597944(1-10)Online publication date: 20-May-2014
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  1. CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques

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      Published In

      cover image Journal of Systems Architecture: the EUROMICRO Journal
      Journal of Systems Architecture: the EUROMICRO Journal  Volume 56, Issue 10
      October, 2010
      57 pages

      Publisher

      Elsevier North-Holland, Inc.

      United States

      Publication History

      Published: 01 October 2010

      Author Tags

      1. Dynamic binary translation
      2. Hardware/software collaboration
      3. Multi-source
      4. Runtime profiling

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      View all
      • (2019)Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translatorJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2019.07.00898:C(173-190)Online publication date: 1-Sep-2019
      • (2014)SPTUProceedings of International Conference on Systems and Storage10.1145/2611354.2611368(1-12)Online publication date: 30-Jun-2014
      • (2014)DTTProceedings of the 11th ACM Conference on Computing Frontiers10.1145/2597917.2597944(1-10)Online publication date: 20-May-2014
      • (2013)SPIREACM SIGPLAN Notices10.1145/2517326.245151648:7(1-12)Online publication date: 16-Mar-2013
      • (2013)SPIREProceedings of the 9th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments10.1145/2451512.2451516(1-12)Online publication date: 16-Mar-2013

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