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An efficient hardware accelerator architecture for implementing fast IMDCT computation

Published: 01 August 2010 Publication History

Abstract

In this paper, a new fast inverse modified discrete cosine transform (IMDCT) algorithm and an efficient hardware accelerator architecture are proposed. The proposed fast algorithm is derived from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCT-IV/DST-IV) decomposition algorithm. After transformations of DST-IV to DCT-IV and DCT-IV to IDCT-II, the computational items are further recombined to share hardware resources. Experimental results show that the proposed algorithm's computational cycles are decreased by 20% and 51%, respectively compared with two other reported fast algorithms. By employing resource sharing and multiplexing techniques, the proposed hardware accelerator reduces 24% and 48% of transistors compared with two other ones, respectively.

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Cited By

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  • (2012)Generalized fast mixed-radix algorithm for the computation of forward and inverse MDCTsSignal Processing10.1016/j.sigpro.2011.08.00192:2(363-373)Online publication date: 1-Feb-2012

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Information

Published In

cover image Signal Processing
Signal Processing  Volume 90, Issue 8
August, 2010
303 pages

Publisher

Elsevier North-Holland, Inc.

United States

Publication History

Published: 01 August 2010

Author Tags

  1. Hardware accelerators
  2. Inverse modified discrete cosine transform
  3. Type-II inverse discrete cosine transform
  4. Type-IV discrete cosine/sine transform

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  • (2012)Generalized fast mixed-radix algorithm for the computation of forward and inverse MDCTsSignal Processing10.1016/j.sigpro.2011.08.00192:2(363-373)Online publication date: 1-Feb-2012

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