An ultra-compact and high-speed FFT-based large-integer multiplier for fully homomorphic encryption using a dual spike-based arithmetic circuit over GF(p)
References
Index Terms
- An ultra-compact and high-speed FFT-based large-integer multiplier for fully homomorphic encryption using a dual spike-based arithmetic circuit over GF(p)
Recommendations
A novel parallel multiplier using spiking neural P systems with dendritic delays
High performance spiking neural multiplier.Parallel input data processing in SN P systems.Scalable parallel architecture based on SN P systems. In the last 10 years, there has been a considerable increase in the number of studies on the development of ...
An efficient hardware implementation of a novel unary Spiking Neural Network multiplier with variable dendritic delays
We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of the ...
Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers
DSD '13: Proceedings of the 2013 Euromicro Conference on Digital System DesignThis work describes FPGA hardware architectures of GF(2m) multipliers being more compact than a bit-serial multiplier and outperforming software counterparts. The proposed multiplier is more compact than a hardware implementation of the bit-serial ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
Publisher
Elsevier Science Publishers B. V.
Netherlands
Publication History
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0