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Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type GAA MOSFETs

Published: 19 September 2024 Publication History

Abstract

Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type gate-all-around MOSFETs (GAA MOSFETs) are reported in this work through experimental and numerical simulation data. N-type GAA MOSFETs of varying lengths (60 nm to 160 nm) and widths (20 nm to 42 nm) are fabricated and measured to extract key electrical parameters like ON current, ON-to-OFF current ratio, threshold voltage, DIBL, and subthreshold swing. Moreover, the influence of tensile strain on carrier transport parameters in the buried Si layer is examined in this work. The Ge mole fraction in SiGe is raised from 0.2 to 0.3, and the corresponding changes in XX-stress, and current density are analyzed using a TCAD simulator. The performance of the proposed device has also been compared with unstrained SiGe/Si, all Si, and SiGe-based GAA MOSFETs.

References

[1]
IEEE, International Roadmap for Devices and Systems. [Online], 2021, Available: https://irds.ieee.org/images/files/pdf/2021/2021IRDS_ES.pdf.
[3]
Samsung Announces 3nm Process Node, the First with Gate-All-Around FETs. Available: https://www.eejournal.com/article/samsung-announces-3nm-process-node-the-first-with-gate-all-around-fets/.
[4]
TSMC to implement gate-all-around (GAAFET) transistors on the 2 nm nodes by 2023. Available: https://www.notebookcheck.net/TSMC-to-implement-gate-all-around-GAAFET-transistors-on-the-2-nm-nodes-by-2023.494850.0.html.
[5]
L. Cao, Q. Zhang, Y. Luo, J. Gu, W. Gan, P. Lu, J. Yao, H. Xu, P. Zhao, K. Luo, Y. Wu, Novel channel-first fishbone FETs with symmetrical threshold voltages and balanced driving currents using single work function metal process, IEEE Trans. Elect. Devices 69 (11) (2022) 5971.
[6]
S.C. Rustagi, N. Singh, W.W. Fang, K.D. Buddharaju, S.R. Omampuliyur, S.H.G. Teo, C.H. Tung, G.Q. Lo, N. Balasubramanian, D.L. Kwong, CMOS inverter based on gate-all-around silicon-nanowire MOSFETs fabricated using top-down approach, IEEE Elect. Device Lett. 28 (11) (2007) 1021.
[7]
V. Pott, K.E. Moselund, D. Bouvet, L. De Michielis, A.M. Ionescu, Fabrication and characterization of gate-all-around silicon nanowires on bulk silicon, IEEE Trans. Nanotechnol. 7 (6) (2008) 733.
[8]
A. Maniyar, P.S.T.N. Srinivas, P.K. Tiwari, K.S. Chang-Liao, Impact of process-induced inclined sidewalls on gate-induced drain leakage (GIDL) current of nanowire GAA MOSFETs, IEEE Trans. Elect. Devices 69 (9) (2022) 4815.
[9]
J. Batakala, R.S. Dhar, Effect of channel material on the performance parameters of GAA MOSFET, J. Nano-Elect. Phys. 14 (2) (2022).
[10]
M.J.H. Van Dal, G. Vellianitis, et al., Ge CMOS gate stack and contact development for vertically stacked lateral nanowire FETs, in: 2018 IEEE International Electron Devices Meeting (IEDM) 21-1, 2018.
[11]
Hiroaki Arimura, Geert Eneman, et al., Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFETIn, in: 2018 IEEE International Electron Devices Meeting, 2018, IEDM 21–2.
[12]
C.H. Lee, S. Mochizuki, G. Southwick Richard, et al., A comparative study of strain and Ge content in Si 1− x Ge x channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs in 2017, in: IEEE International Electron Devices Meeting (IEDM) 37–2 , 2017.
[13]
Yeap Geoffrey, S.S. Lin, et al., 5nm cmos production technology platform featuring full-fledged euv, and high mobility channel finfets with densest 0.021 μm 2 sram cells for mobile soc and high performance computing applications in 2019, in: IEEE International Electron Devices Meeting (IEDM), 2019, pp. 36–37.
[14]
Yu-Shiang Huang, Chung-En Tsai, et al., First demonstration of uniform 4-Stacked Ge 0.9 Sn 0.1 nanosheets with record ION= 73μA at V OV= V DS=-0.5 V and low noise using double Ge 0.95 Sn 0.05 caps, dry etch, low channel doping, and high S/D doping in 2020, IEEE Int. Elect. Dev. Meet. (IEDM) (2020) 2.
[15]
C.E. Tsai, Y.C. Liu, C.T. Tu, B.W. Huang, S.R. Jan, Y.R. Chen, J.Y. Chen, et al., Highly stacked 8 Ge0.9Sn0.1NanosheetpFETs with ultrathin bodies (∼ 3 nm) and thick bodies (∼ 30 nm) featuring the respective record ION/IOFF of 1.4 x107 and record ION of 92 μA at Vov= VDS=− 0.5 V by CVD epitaxy and dry etching in, in: Proceedings of the 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, p. 11.
[16]
Wei-Ren Chen, Dun-Bao Ruan, Kuei-Shu Chang-Liao, Hao-Yan Wang, Guang-Li Luo, Yu-Chuan Chiu, Ting-Kai Kuan, Po-Tsun Liu, Enhanced performance for SiGe/Si gate-all-around field-effect-transistor with Ge condensation using supercritical fluid treatment, in: 2023 Silicon Nanoelectronics Workshop (SNW), 2023, p. 25.
[17]
Yao-Jen Lee, Fu-Ju Guang-Li Luo, Min-Cheng Chen Hou, Chih-Chao Yang, Chang-Hong Shen, Wu Wen-Fa, Jia-Min Shieh, Wen-Kuan Yeh Ge, GAA FETs and TMD finfets for the applications beyond Si—A review, IEEE J. Elect. Dev. Soc. 4 (2016) 286.
[18]
C.W. Liu, Yen-Ting Chen, Shu-Han Hsu, Gate-all-around Ge FETs, ECS Trans. 64 (2014) 317.
[19]
Mingshan Liu, Yannik Junk, Yi Han, Dong Yang, JinHee Bae, Marvin Frauenrath, Jean-Michel Hartmann, et al., Vertical GeSn nanowire MOSFETs for CMOS beyond silicon, Commun. Eng. 2 (2023) 7.
[20]
Ching-Ru Yang Yi-JuYao, Ting-Yu Tseng, Heng-Jia Chang, Tsai-Jung Lin, Guang-Li Luo, Fu-Ju Hou, Yung-Chun Wu, Kuei-Shu Chang-Liao, High performance P-and N-Type SiGe/Si strained super-lattice FinFET and CMOS inverter: comparison of Si and SiGeFinFET, Nanomaterials 13 (2023) 1310.
[21]
S. Conti, S. Saberi-Pouya, M. Virgilio APerali, F.M. Peeters, A.R. Hamilton, D. GScappucci, Neilson Electron–hole superfluidity in strained Si/Ge type II heterojunctions, npj Quantum Mater. 6 (2021) 41.
[22]
S. Gupta, V. Moroz, L. Smith, Q. Lu, K CSaraswat 7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn, IEEE Trans. Elect. Devices 611222-30 (2014).
[23]
S.E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.H. Jan, A 90-Nm Logic technology featuring strained-Silicon, IEEE Trans. Elect. Devices (2004) 511790–511797.
[24]
R. Tiwari, N. Parihar, K. Thakor, H.Y. Wong, S. Motzny, M. Choi, V. Moroz, S. Mahapatra, A 3-D TCAD framework for NBTI—part I: implementation details and FinFET channel material impact, IEEE Trans. Elect. Devices 66 (2019) 2086–2092.
[25]
S.E. Thompson, S. Suthram, Y. Sun, G. Sun, S. Parthasarathy, M. Chu, T. Nishida, Future of strained Si/semiconductors in nanoscale MOSFETs, 2006 Int. Elect. Dev. Meet. (2006) 1–4.
[26]
S. Sun, J.S. Yuan, Z.J. Shen, Performance of trench power MOSFET with strained Si/SiGe multilayer channel, IEEE Trans. Elect. Dev. 58 (2011) 1517.
[27]
D.B. Ruan, K.S. Chang-Liao, W.Y. Hsu, S.H. Yi, Y.J. Lee, Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer, Vacuum 179 (2020).
[28]
D.B. Ruan, K.S. Chang-Liao, H.I. Yeh, F.Y. Chu, K.C. Yang, P.C. Wu, E.R. Hsieh, Oxygen diffusion barrier on interfacial layer formed with remote NH3 plasma treatment, Surf. Coat. Technol. 423 (2021).
[29]
D.B. Ruan, K.S. Chang-Liao, W.Y. Hsu, S.H. Yi, Improved electrical characteristics of Ge nMOSFET with suitable nitrogen content in starting interfacial layer, Vacuum 181 (2020).
[30]
D.B. Ruan, K.S. Chang-Liao, C.C. Liu, Y.H. Chien, Y.J. Lee, Effects of pre-and post-microwave annealing treatments on pGe MOS device, Surf. Coat. Technol. 423 (2021).
[31]
S. Bangsaruntip, G.M. Cohen, A. Majumdar, Y. Zhang, S.U. Engelmann, N.C.M. Fuller, L.M. Gignac, S. Mittal, J.S. Newbury, M. Guillorn, T. Barwicz, December., High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling, in: In 2009 IEEE International Electron Devices Meeting (IEDM), IEEE, 2009, pp. 1–4.
[32]
W.R. Chen, D.B. Ruan, K.S. Chang-Liao, H.Y. Wang, G.L. Luo, Y.C. Chiu, T.K. Kuan, P.T. Liu, Enhanced performance for SiGe/Si Gate-all-around field-effect- transistor with Ge condensation using supercritical fluid treatment, in: 2023 Silicon Nanoelectronics Workshop (SNW), 2023, pp. 25–26.
[33]
T. Sentaurus, Version O-2018.06, in: Synop., Mountain View, CA, USA, Tech. Rep, 2018, [Online]. Available: https://www.synopsys.com/ silicon/tcad/device- simulation/sentaurus-device.html.
[34]
: Visual TCAD software [Online]. https://cogenda.com/article/downloads.
[35]
E.X. Wang, P. Matagne, L. Shifren, B. Obradovic, R. Kotlyar, S. Cea, M. Stettler, M.D. Giles, Physics of hole transport in strained silicon MOSFET inversion layers, IEEE Transactions on Electron Devices 53 (8) (2006) 1840.
[36]
S. Sun, J.S. Yuan, Performance of trench power MOSFET with strained Si/SiGe multilayer channel, IEEE transactions on electron devices 58 (5) (2011) 1517.
[37]
T.P. Dash, S. Dey, S. Das, E. Mohaptra, J. Jena, C.K. Maiti, Stress Tuning in NanoScaleFinFETs at 7nm, In 2018 IEEE Electron Devices Kolkata Conference (EDKCON) (2018) 166.
[38]
S. Gupta, V. Moroz, L. Smith, Q. Lu, K.C. Saraswat, 7-nm FinFET CMOS design enabled by stress engineering using Si, Ge, and Sn, IEEE transactions on Electron Devices 61 (5) (2014) 1222.
[39]
S. Sun, J.S. Yuan, Performance of trench power MOSFET with strained Si/SiGe multilayer channel, IEEE transactions on electron devices 58 (5) (2011) 1517.
[40]
Y.J. Yao, C.R. Yang, T.Y. Tseng, H.J. Chang, T.J. Lin, G.L. Luo, F.J. Hou, Y.C. Wu, High- Performance P-and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGeFinFET, Nanomaterials 13 (8) (2023) 1310.

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  1. Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type GAA MOSFETs
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                Published In

                cover image Microelectronic Engineering
                Microelectronic Engineering  Volume 292, Issue C
                Sep 2024
                100 pages

                Publisher

                Elsevier Science Ltd.

                United Kingdom

                Publication History

                Published: 19 September 2024

                Author Tags

                1. Fabrication
                2. GAA MOSFET
                3. Strained- silicon
                4. Short-Channel effects

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