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research-article

Performance evaluation of modified mesh-based NoC architecture

Authors:

B. Naresh Kumar Reddy,

Subrat KarAuthors Info & Claims

Volume 104, Issue PA

https://doi.org/10.1016/j.compeleceng.2022.108404

Published: 01 December 2022 Publication History

Abstract

With the advancement of technology in the field of VLSI, it is possible to integrate several computing elements onto a single chip. The performance of these single bus-based models still suffers from scalability on large-scale platforms. Therefore, network-on-chip (NoC) architecture integrating multiple cores in a single chip has emerged as an alternative. An efficient mapping is one of the most essential activities in high-performance multi-processor architectures. This research paper proposes an efficient core mapping and modified 2-D mesh NoC architecture. Every core is connected to the two routers via a network interface. In an efficient core mapping algorithm, the mapping region is selected based on Core Efficient Region (CER), which can improve the processor performance. The proposed core mapping algorithm is applied to the multimedia benchmarks. The experimental results show that the efficient core mapping algorithm outperforms the communication energy and performance when compared with other recent mapping algorithms.

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Highlights

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In this paper, an optimized core mapping algorithm is proposed, and a modified 2-D mesh NoC architecture is introduced.

•

In modified 2-D mesh NoC every core is connected with the two routers.

•

An optimized core mapping algorithm, which maps the cores on modified NoC based on the ACG using core efficient region.

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The optimized core mapping algorithm was applied to multimedia benchmarks and evaluated communication energy and CPU time.

References

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Cited By

Mazumdar SScionti AZuckerman SPortero A(2023)NoC-based hardware software co-design framework for dataflow thread managementThe Journal of Supercomputing10.1007/s11227-023-05335-879:16(17983-18020)Online publication date: 11-May-2023
https://dl.acm.org/doi/10.1007/s11227-023-05335-8

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Performance evaluation of modified mesh-based NoC architecture

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Information & Contributors

Information

Published In

cover image Computers and Electrical Engineering

Computers and Electrical Engineering Volume 104, Issue PA

Dec 2022

509 pages

ISSN:0045-7906

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Elsevier Ltd.

Publisher

Pergamon Press, Inc.

United States

Publication History

Published: 01 December 2022

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Cited By

Mazumdar SScionti AZuckerman SPortero A(2023)NoC-based hardware software co-design framework for dataflow thread managementThe Journal of Supercomputing10.1007/s11227-023-05335-879:16(17983-18020)Online publication date: 11-May-2023
https://dl.acm.org/doi/10.1007/s11227-023-05335-8

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