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article

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Authors:

K. Rahimunnisa,

P. Karthigaikumar,

Soumiya Rasheed,

S. SureshKumarAuthors Info & Claims

Security and Communication Networks, Volume 7, Issue 11

Pages 2225 - 2236

https://doi.org/10.1002/sec.651

Published: 01 November 2014 Publication History

Abstract

This paper presents high throughput architecture for the hardware implementation of Advanced Encryption Standard algorithm. Advanced Encryption Standard is the industry standard crypto algorithm for encryption and is used for protecting secret information. This work is mainly targeted for low-cost embedded applications. This paper introduces parallel operation in the folded architecture to obtain better throughput. The design is coded in Very High-speed Integrated Circuit Hardware Description Language. Timing simulation is performed to verify the functionality of the designed circuit. The proposed structure is implemented in Virtex-6 XC6VLX75T FPGA device. This work gives a high throughput of 37.1Gb/s with a maximum frequency of 505.5MHz, which is 20% higher than the maximum throughput reported in the literature. Copyright © 2012 John Wiley & Sons, Ltd.

References

[1]

Federal Information Processing Standards Publication 197 November 26, Announcing the Advanced Encryption Standard AES, 2001.

[2]

Mali M, Novak F, Biasizzo A. Hardware implementation of AES algorithm. Journal of Electrical Engineering 2005; Volume 56 Issue 9-10: pp.265-269.

[3]

Chodowiec P, Gaj K. Very compact FPGA implementation of the AES algorithm. Proc. of Cryptographic Hardware and Embedded System Workshop, 2003; pp.319-333.

[4]

Granado-Criado JM. A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. Integration, the VLSI Journal 2010; Volume 43 Issue 1: pp.72-80.

[5]

Hamalainen P, Alho T, Hannikainen M. Design and implementation of low-area and low-power AES encryption hardware core. 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, 2006; pp.577-583.

[6]

Alaoui Ismaili ZEA, Moussa A. Self-partial and dynamic reconfiguration implementation for AES using FPGA. IJCSI International Journal of Computer Science Issues 2009; Volume 2: pp.33-40.

[7]

Rouvroy G, Standaert F-X. Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. Proceeding of International Conference on Information Technology: Coding and Computing, Vol. 2, 2004; pp.583-587.

[8]

Standaert F-X, Rouvroy G. Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs. <bookSeriesTitle>Lecture Notes in Computer Science</bookSeriesTitle>, Vol. 2779/2003, Cologne, Germany</publisherLoc>: <publisherLoc>Springer, 2003; pp.334-350.

[9]

Hodjat A, Verbauwhede I. A 21.54 Gbits/s fully pipelined AES processor on FPGA. Proceeding of 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2004; pp.308-309.

[10]

Fan C-P, Hwang J-K. FPGA implementations of high throughput sequential and fully pipelined AES algorithm. International Journal of Electrical Engineering 2008; Volume 15 Issue 6: pp.447-455.

[11]

Yoo SM, Kotturi D, Pan DW, Blizzard J. An AES crypto chip using a high-speed parallel pipelined architecture. Microprocessors and Microsystems 2005; Volume 29 Issue 7: pp.317-326.

[12]

Zhang X, Parthi KK. High-speed VLSI architecture for AES algorithm. IEEE Transactions on Very Large Scale Integration VLSI Systems 2004; Volume 12 Issue 9: pp.957-967.

[13]

Liberatori MC, Bonadero JC. AES-128 cipher minimum area, low cost FPGA implementation. Lattin American Applied Research 2007; Volume 37: pp.71-77.

[14]

Chittu C, Chien D, Chien C, Verbauwhede I, Chang F. A hardware implementation in FPGA of the Rijndael algorithm. Proceeding of 45th Midwest Symposium on Circuits and Systems, Vol. 1, 2002; pp.507-510.

[15]

Fischer V, Drutarovsky M. Two methods of Rijndael implementation in reconfigurable hardware. Proc. CHES 2001, Paris, France, May 2001; pp.77-92.

[16]

Rodriguez Henriquez F, Saquib NA, Diaz-Perez A. 4.2 Gbits/sec single chip FPGA implementation of the AES algorithm. Electronics Letters 2003; Volume 39 Issue 15: pp.1115-1116.

[17]

Sklavos N, Koufopavlou O. Architectures and VLSI implementations of the AES proposal Rijndael. IEEE Transactions on Computers 2002; Volume 51 Issue 12: pp.1454-1459.

[18]

Hodjat A, Verbauwhede I. Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. IEEE Transactions on Computers 2006; Volume 55 Issue 4: pp.366-372.

Digital Library

[19]

Kuo H, Verbauwhede I. Architectural optimization for a 1.82 Gbits/sec VLSI implementation of the AES Rijndael algorithm. Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems, 2001; pp.51-64.

[20]

McLoone M, McCanny JV. Rijndael FPGA implementation utilizing look-up tables. Journal of Signal Processing Systems 2001; Volume 34 Issue 3: pp.349-360.

[21]

Sirin Kumari M, Mahesh Kumar D, Rama Devi Y. High throughput-less area efficient FPGA Implementation of block cipher AES algorithm. International Conference On Advanced Computing, Communication and Networks, 2011; pp.484-489.

[22]

Rais MH, Qasim SM. Efficient hardware realization of advanced encryption standard algorithm using Virtex-5 FPGA. IJCSNS International Journal of Computer Science and Network Security 2009; Volume 9 Issue 9: pp.59-63.

[23]

Bulens P, Standaert F-X, Quisquater J-J, Pellegrin P, Rouvroy G. Implementation of the AES-128 on Virtex-5 FPGAs. In AFRICACRYPT 2008, <bookSeriesTitle>Lecture Notes in Computer Science</bookSeriesTitle>, Vol. 5023. Springer: Casablanca, Morocco, 2008; pp.16-26.

[24]

Lemsitzer S, Wolkerstorfer J, Felbert N, Braendli M. Multi-gigabit GCM-AES architecture optimized for FPGAs. Workshop on Cryptographic Hardware and Embedded Systems - CHES'07, 2007; pp.227-238.

[25]

Good, Benaissa M. AES on FPGA from the fastest to the smallest. In Cryptographic Hardware and Embedded Systems, CHES 2005. Springer: Edinburgh, UK, 2005; pp.427-440.

[26]

Kotturi D, Yoo SM, Blizzard J. AES crypto chip utilizing high-speed parallel pipelined architecture. IEEE International Symposium on Circuits and Systems, vol. 5, 2005; pp.4653-4656.

[27]

Aziz A, Ikram N. Hardware implementation of AES-CCM for robust secure wireless network. "http://icsa.cs.up.ac.za/issa/2005/Proceedings/Research/069_Article.pdf".

[28]

Zambreno J, Nguyen D, Choudary A. Exploring area/delay tradeoffs in an AES FPGA implementation. In Proceeding of Field-Programmable Logic and Applications, LNCS. Springer, 2004; pp.575-585.

[29]

Farhan SM, Jamal H, Rahmatullah M. High data rate 8-bit crypto-processor. ISSA Enabling tomorrow Conference, Gallagher Estate, Midrand, South Africa, 2004.

[30]

Hodjat A, Verbauwhede I. A 21.54 Gbits/s fully pipelined AES processor on FPGA. IEEE Symposium on Field-Programmable Custom Computing Machines, 2004; pp.308-309.

[31]

Sever R, Ismailglu AN, Tekmen YC, Askar M, Okcan B. A high speed FPGA implementation of the Rijndael algorithm. Euromicro Symposium on Digital System Design, 2004; pp.358-362.

[32]

Wang SS, Ni WS. An efficient FPGA implementation of advanced encryption standard algorithm. International Symposium on Circuits and Systems, Vol. 2, 2004; pp.II-597-600.

[33]

Jarvinen KU, Tommiska MT, Skytta JO. A fully pipelined memory less 17.8 Gbps AES-128 encryptor. International Symposium on Field Programmable Gate Arrays, 2003; pp.207-215.

[34]

Saggese GP, Mazzeo A, Mazzocca N, Strollo AGM. An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In FPL 2003, <bookSeriesTitle>LNCS</bookSeriesTitle> Vol. 2778, Lisbon, Portugal, 2003; 292- pp.302.

[35]

Vu K, Zier D. FPGA implementation AES for CCM mode encryption using Xilinx Spartan-II. ECE-679. Oregon State University, Spring, 2003.

[36]

Saqib NA, Henriquez FR, Perez AD. AES algorithm implementation - an efficient approach for sequential and pipeline architectures. The Fourth Mexican International Conference on Computer Science, Sep. 2003; pp.126-130.

[37]

Standaert F-X, Rouvroy G, Quisquater J-J, Legat J-D. A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. 11th ACM International Symposium on Field-Programmable Gate Arrays FPGA'03, 2003; pp.216-224.

[38]

Chitu C, Chien D, Chien C, Verbauwhede I, Chang F. A hardware implementation in FPGA of the Rijndael algorithm. The 45th Midwest Symposium on Circuits and Systems, vol. 1, 2002; pp.I-507-10.

[39]

Helion. "http://www.heliontech.com"

[40]

Manavski SA. CUDA compatible GPU as an efficient hardware accelerator for AES Cryptography. IEEE International Conference on Signal Processing and Communications ICSPC, 2007; pp.65-68.

[41]

Harrison O, Waldron J. AES encryption implementation and analysis on commodity graphics processing units. Cryptographic Hardware and Embedded Systems CHES, 2007; pp.209-226.

[42]

Wollinger TJ, Wang M, Guajardo J, Paar C. How well are high-end DSPs suited for the AES algorithms? 3rd Advanced Encryption Standard Candidate Conference, 2000; pp.94-105.

Cited By

Priya SKarthigaikumar PTeja N(2022)FPGA implementation of AES algorithm for high speed applicationsAnalog Integrated Circuits and Signal Processing10.1007/s10470-021-01959-z112:1(115-125)Online publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1007/s10470-021-01959-z
Jamuna Rani DEmalda Roslin S(2021)Optimized Implementation of Gift CipherWireless Personal Communications: An International Journal10.1007/s11277-021-08325-2119:3(2185-2195)Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1007/s11277-021-08325-2
Manjith B.C. Ramasubramanian N. (2020)Securing AES Accelerator from Key-Leaking Trojans on FPGAInternational Journal of Embedded and Real-Time Communication Systems10.4018/IJERTCS.202007010511:3(84-105)Online publication date: 1-Jul-2020
https://dl.acm.org/doi/10.4018/IJERTCS.2020070105
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FPGA implementation of AES algorithm for high throughput using folded parallel architecture

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Published In

cover image Security and Communication Networks

Security and Communication Networks Volume 7, Issue 11

November 2014

596 pages

ISSN:1939-0114

EISSN:1939-0122

Issue’s Table of Contents

Publisher

John Wiley & Sons, Inc.

United States

Publication History

Published: 01 November 2014

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Cited By

Priya SKarthigaikumar PTeja N(2022)FPGA implementation of AES algorithm for high speed applicationsAnalog Integrated Circuits and Signal Processing10.1007/s10470-021-01959-z112:1(115-125)Online publication date: 1-Jul-2022
https://dl.acm.org/doi/10.1007/s10470-021-01959-z
Jamuna Rani DEmalda Roslin S(2021)Optimized Implementation of Gift CipherWireless Personal Communications: An International Journal10.1007/s11277-021-08325-2119:3(2185-2195)Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1007/s11277-021-08325-2
Manjith B.C. Ramasubramanian N. (2020)Securing AES Accelerator from Key-Leaking Trojans on FPGAInternational Journal of Embedded and Real-Time Communication Systems10.4018/IJERTCS.202007010511:3(84-105)Online publication date: 1-Jul-2020
https://dl.acm.org/doi/10.4018/IJERTCS.2020070105
Desai LMali S(2018)Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data HidingVLSI Design10.1155/2018/48047292018Online publication date: 27-Sep-2018
https://dl.acm.org/doi/10.1155/2018/4804729
Amine FAbdelkader G(2017)Hybrid Approach of Modified AESInternational Journal of Organizational and Collective Intelligence10.4018/IJOCI.20171001057:4(83-93)Online publication date: 1-Oct-2017
https://dl.acm.org/doi/10.4018/IJOCI.2017100105
Priya SKarthigaikumar PSiva Mangai NKirti Gaurav Das P(2017)An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-BoxWireless Personal Communications: An International Journal10.1007/s11277-016-3385-794:4(2259-2273)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s11277-016-3385-7
Rao MNewe TGrout IMathur A(2016)An FPGA-based reconfigurable IPSec AH core with efficient implementation of SHA-3 for high speed IoT applicationsSecurity and Communication Networks10.1002/sec.15339:16(3282-3295)Online publication date: 10-Nov-2016
https://dl.acm.org/doi/10.1002/sec.1533
Mohd BHayajneh TKhalaf ZAhmad Yousef K(2016)Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementationSecurity and Communication Networks10.1002/sec.14799:13(2200-2216)Online publication date: 10-Sep-2016
https://dl.acm.org/doi/10.1002/sec.1479
Soltani ASharifian S(2015)An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGAMicroprocessors & Microsystems10.1016/j.micpro.2015.07.00539:7(480-493)Online publication date: 1-Oct-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.07.005

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