PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
Pages 88 - 100
Abstract
Arithmetic accelerators are always in demand for fast computations and logic operations. Here, posit arithmetic plays an important role; it outperforms the traditional IEEE-754 floating-point in terms of accuracy and dynamic range. This paper proposes efficient sequential architectures for the posit adder/subtractor and multiplier that work according to the desired bit size of operands. Here, 32-bit architectures with different exponent sizes (ES) have been designed with a control unit. FPGA implementations of these architectures have been performed on the Xilinx Virtex-7 xc7vx330t-3ffg1157 and the Zynq UltraScale + MPSoC ZCU102 device. In comparison with the existing work, it is observed that the datapath delay is lowered by 64.64% for the 32-bit adder and 52.66% for the 32-bit multiplier on the Xilinx Virtex-7 FPGA device. Furthermore, the area-delay (AD) product is reduced by 52.69% and 69.30% for the 32-bit posit adder and multiplier, respectively. In addition, the proposed design has reduced dynamic power than the existing architectures.
References
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Information
Published In
Mar 2023
198 pages
ISBN:978-3-031-32179-5
DOI:10.1007/978-3-031-32180-1
© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 12 May 2023
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