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Six Shades of AES

Published: 09 July 2019 Publication History

Abstract

Recently there have been various attempts to construct light weight implementations of the AES-128 encryption and combined encryption/ decryption circuits [2, 13]. However no known lightweight circuit exists for AES-192 and AES-256, the variants of AES that use longer keys. Investing in lightweight implementations of these ciphers is important as we enter the post quantum era in which security is, by a rule of the thumb, scaled down to the square-root of the size of the keyspace. In this paper, we propose a single circuit that is able to offer functionalities of both encryption and decryption for AES-128/192/256. Our circuit operates on an 8-bit datapath and occupies around 3672 GE of area in silicon. We outline the challenges that presented themselves while performing the combinatorial optimization of circuit area and the methods we used to solve them.

References

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Jean J, Moradi A, Peyrin T, and Sasdrich P Fischer W and Homma N Bit-sliding: a generic technique for bit-serial implementations of spn-based primitives Cryptographic Hardware and Embedded Systems – CHES 2017 2017 Cham Springer 687-707
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Mathew S et al. 340 mV-1.1V, 289 Gbps/W, 2090-gate nanoAES hardware accelerator with area-optimized encrypt/decrypt GF() polynomials in 22 nm tri-gate CMOS IEEE J. Solid-State Circ. 2015 50 1048-1058
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Published In

cover image Guide Proceedings
Progress in Cryptology – AFRICACRYPT 2019: 11th International Conference on Cryptology in Africa, Rabat, Morocco, July 9–11, 2019, Proceedings
Jul 2019
450 pages
ISBN:978-3-030-23695-3
DOI:10.1007/978-3-030-23696-0

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 09 July 2019

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