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Article

Efficient system-on-chip energy management with a segmented bloom filter

Authors:

Hsien-Hsin S. LeeAuthors Info & Claims

ARCS'06: Proceedings of the 19th international conference on Architecture of Computing Systems

Pages 283 - 297

https://doi.org/10.1007/11682127_20

Published: 13 March 2006 Publication History

Abstract

As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss in a long-latency cache becomes crucial in an embedded system-on-chip(SOC) platform to perform microarchitecture-level energy management. Counting Bloom filters are simple and fast structures that can eliminate associative lookup in a huge lookup space. This paper presents an innovative segmented design of the counting Bloom filter which can save SOC energy by detecting misses aiming at a cache level before the memory. The filter presented is successful in filtering out 89% of L2 cache misses and thus helps in reducing L2 accesses by upto 30%. This reduction in L2 Cache accesses and early triggering of energy management processes lead to an overall SOC energy savings by up to 9%.

References

[1]

Bloom, B.H.: Space/time trade-offs in hash coding with allowable errors. Communications of the ACM 13(4) (1970)

Digital Library

[2]

Fan, L., Cao, P., Almeida, J., Broder, A.: Summary cache: A scalable wide-area web cache sharing protocol. IEEE/ACM Transactions on Networking 8(3) (2000) 281-293

Digital Library

[3]

Burger, D., Austin, T.M.: The simplescalar tool set, version 2.0. Technical Report 1342, Computer Science Department, University of Wisconsin-Madison and MicroComputer Research Labs, Intel Corporation (1997)

[4]

Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: the IEEE 4th Annual Workshop on Workload Characterization, Austin, TX (2001)

Digital Library

[5]

Fan, D., Tang, Z., Huang, H., Gao, G.R.: An energy efficient tlb design methodology. In: Proceedings of the International Symposium on Low Power Electronics and Design. (2005)

Digital Library

[6]

Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy caches: Simple techniques for reducing leakage power. In: Proceedings of the 29th Annual International Symposium on Computer Architecture. (2002)

Digital Library

[7]

Artisan: Sram libraries. http://www.artisan.com (2005)

[8]

Border, A., Mitzenmacher, M.: Network application of bloom filters: A Survey. In: 40th Annual Allerton Conference on Communication, Control, and Computing. (2002)

[9]

Rhea, S., Kubiatowicz, J.: Probabilistic location and routing. In: IEEE INFOCOM' 02. (2002)

[10]

Dharmapurikar, S., Krishnamurthy, P., Sproull, T., Lockwood, J.: Deep packet inspection using parallel bloom filters. In: IEEE Hot Interconnects 12. (2003)

[11]

Kumar, A., Xu, J., Wang, J., Spatschek, O., Li, L.: Space-code bloom filter for efficient per-flow traffic measurement. In: Proc. IEEE INFOCOM. (2004)

[12]

Chang, F., Feng, W., Li, K.: Approximate caches for packet classification. In: Proc. IEEE INFOCOM. (2004)

[13]

Cohen, S., Matias, Y.: Spectral bloom filters. In: Proceedings of the 2003 ACM SIGMOD International Conference on Management of Data. (2003)

Digital Library

[14]

Akkary, H., Rajwar, R., Srinivasan, S.T.: Checkpoint processing and recovery: Towards scalable large instruction window processors. In: Proceedings of the 36th International Symposium for Microarchitecture. (2003)

Digital Library

[15]

Sethumadhavan, S., Desikan, R., Burger, D., Moore, C.R., Keckler, S.W.: Scalable hardware memory disambiguation for high ilp processors. In: Proceedings of the 36th International Symposium for Microarchitecture. (2003)

Digital Library

[16]

Roth, A.: Store vulnerability window (svw): Re-execution filtering for enhanced load optimization. In: Proceedings of the 32th International Symposium on Computer Architecture (ISCA-05). (2005)

Digital Library

[17]

Moshovos, A., Memik, G., Falsafi, B., Choudhary, A.: Jetty: Snoop filtering for reduced power in smp servers. In: Proceedings of International Symposium on High Performance Computer Architecture (HPCA-7). (2001)

[18]

Peir, J.K., Lai, S.C., Lu, S.L., Stark, J., Lai, K.: Bloom filtering cache misses for accurate data speculation and prefetching. In: Proceedings of the 16th International Conference of Supercomputing. (2002) 189-198

Digital Library

[19]

Mehta, N., Singer, B., Bahar, R.I., Leuchtenburg, M., Weiss, R.: Fetch halting on critical load misses. In: Proceedings of the The 22nd International Conference on Computer Design. (2004)

Digital Library

[20]

Memik, G., Reinman, G., Mangione-Smith, W.H.: Just say no: Benefits of early cache miss determination. In: Proceedings of the Ninth International Symposium on High Performance Computer Architecture. (2003)

Digital Library

Cited By

Wang ZLuo CLuo T(2018)Selection Optimization of Bloom Filter-Based Index Services in Ubiquitous Embedded SystemsWeb Services – ICWS 201810.1007/978-3-319-94289-6_15(231-245)Online publication date: 25-Jun-2018
https://dl.acm.org/doi/10.1007/978-3-319-94289-6_15
Ghosh MOzer EFord SBiles SLee HHenkel JKeshavarzi AChang NGhani T(2009)Way guardProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594276(165-170)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594276
Ballapuram CSharif ALee H(2008)Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessorsACM SIGPLAN Notices10.1145/1353536.134629043:3(60-69)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1353536.1346290
Show More Cited By

Efficient system-on-chip energy management with a segmented bloom filter
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Information & Contributors

Information

Published In

cover image Guide Proceedings

ARCS'06: Proceedings of the 19th international conference on Architecture of Computing Systems

March 2006

493 pages

ISBN:3540327657

Editors:
Werner Grass
University of Passau, Innstr. 33, Passau, Germany
,
Bernhard Sick
Faculty of Computer Science and Mathematics - Institute of Computer Architectures, University of Passau, Innstrasse 33, Passau, Germany
,
Klaus Waldschmidt
Faculty of Computer Science and Mathematics - Institute of Computer Architectures, University of Frankfurt/Main, Robert-Mayer-Str. 11-15, Frankfurt, Germany

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 13 March 2006

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Cited By

Wang ZLuo CLuo T(2018)Selection Optimization of Bloom Filter-Based Index Services in Ubiquitous Embedded SystemsWeb Services – ICWS 201810.1007/978-3-319-94289-6_15(231-245)Online publication date: 25-Jun-2018
https://dl.acm.org/doi/10.1007/978-3-319-94289-6_15
Ghosh MOzer EFord SBiles SLee HHenkel JKeshavarzi AChang NGhani T(2009)Way guardProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594276(165-170)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594276
Ballapuram CSharif ALee H(2008)Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessorsACM SIGPLAN Notices10.1145/1353536.134629043:3(60-69)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1353536.1346290
Ballapuram CSharif ALee H(2008)Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessorsACM SIGOPS Operating Systems Review10.1145/1353535.134629042:2(60-69)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1353535.1346290
Ballapuram CSharif ALee H(2008)Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessorsACM SIGARCH Computer Architecture News10.1145/1353534.134629036:1(60-69)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1353534.1346290
Ballapuram CSharif ALee HEggers SLarus J(2008)Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessorsProceedings of the 13th international conference on Architectural support for programming languages and operating systems10.1145/1346281.1346290(60-69)Online publication date: 1-Mar-2008
https://dl.acm.org/doi/10.1145/1346281.1346290
Woo DGhosh MÖzer EBiles SLee HHong SWolf WFlautner KKim T(2006)Reducing energy of virtual cache synonym lookup using bloom filtersProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176783(179-189)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176760.1176783

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