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An approach for the verification of systemc designs using asml

Published: 04 October 2005 Publication History

Abstract

The spectacular advancement in microelectronics resulted in the creation of new system level design languages, such as SystemC, which put fourth new design and verification challenges. In this paper, we present an approach verifying SystemC designs using model checking and assertion based verification. Such verification is enabled through two transformations from SystemC to AsmL (the Abstract State Machines Language) and vice-versa. The soundness of these transformations, proved using abstract interpretation, guarantees the correctness of the model checking results and the validity of the generated assertion monitors (to be checked by simulation). We illustrate our approach on the SystemC/AsmL modeling and verification of the widely used Accelerated Graphics Port (AGP) standard. The verified AGP model can be either refined to implement an AGP core or used to validate existent compatible device.

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Cited By

View all
  • (2024)Deductive Verification of Parameterized Embedded Systems Modeled in SystemCVerification, Model Checking, and Abstract Interpretation10.1007/978-3-031-50521-8_9(187-209)Online publication date: 15-Jan-2024
  • (2021)Combining Forces: How to Formally Verify Informally Defined Embedded SystemsFormal Methods10.1007/978-3-030-90870-6_1(3-22)Online publication date: 20-Nov-2021
  • (2017)Automatic Analysis and Abstraction for Model Checking HW/SW Co-Designs modeled in SystemCACM SIGAda Ada Letters10.1145/3092893.309289536:2(9-17)Online publication date: 10-May-2017
  • Show More Cited By

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Information & Contributors

Information

Published In

cover image Guide Proceedings
ATVA'05: Proceedings of the Third international conference on Automated Technology for Verification and Analysis
October 2005
505 pages
ISBN:3540292098
  • Editors:
  • Doron A. Peled,
  • Yih-Kuen Tsay

Sponsors

  • Ministry of Education, Taiwan
  • Academia Sinica: Academia Sinica
  • National Taiwan University
  • Institute of Information Science: Institute of Information Science
  • National Science Council: National Science Council (Taiwan)

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 04 October 2005

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View all
  • (2024)Deductive Verification of Parameterized Embedded Systems Modeled in SystemCVerification, Model Checking, and Abstract Interpretation10.1007/978-3-031-50521-8_9(187-209)Online publication date: 15-Jan-2024
  • (2021)Combining Forces: How to Formally Verify Informally Defined Embedded SystemsFormal Methods10.1007/978-3-030-90870-6_1(3-22)Online publication date: 20-Nov-2021
  • (2017)Automatic Analysis and Abstraction for Model Checking HW/SW Co-Designs modeled in SystemCACM SIGAda Ada Letters10.1145/3092893.309289536:2(9-17)Online publication date: 10-May-2017
  • (2013)A HW/SW co-verification framework for SystemCACM Transactions on Embedded Computing Systems10.1145/2435227.243525712:1s(1-23)Online publication date: 29-Mar-2013
  • (2011)Formal Analysis of SystemC Designs in Process AlgebraFundamenta Informaticae10.5555/2351788.2351790107:1(19-42)Online publication date: 1-Jan-2011
  • (2008)Model checking SystemC designs using timed automataProceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis10.1145/1450135.1450166(131-136)Online publication date: 19-Oct-2008

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