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The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Authors:

Christophe BobdaAuthors Info & Claims

The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Volume 47, Issue 1

Pages 15 - 31

https://doi.org/10.1007/s11265-006-0017-6

Published: 01 April 2007 Publication History

Abstract

Computer architects have been studying the dynamically reconfigurable computer (Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh, “A Quick Safari through the Reconfiguration Jungle,” in Proc. of the 38th Design Automation Conference, Las Vegas, pp. 127–177, 2001) for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic (Kephart and Chess, Computer, 36:41–52, 2003; IBM Autonomic Computing Initiative, (http://www.research.ibm.com/autonomic/)) and organic computing (Müller-Schloer, von der Malsburg, and Würtz, Inform.-Spektrum, 27:332–336, 2004; The Organic Computing Page, (http://www.organic-computing.org)). Much research work is currently devoted to models for partial hardware module relocation (SPP1148 Reconfigurable Computing Priority Program, (http://www12.informatik.uni-erlangen.de/spprr/)) and dynamically reconfigurable hardware reconfiguration on e.g., FPGA-based platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from (a) a new slot-oriented hardware architecture, (b) a set of novel inter-module communication paradigms, and (c) concepts for dynamic and partial reconfiguration management.

References

[1]

P. Schaumont, I. Verbauwhede, K. Keutzer, and M. Sarrafzadeh, “A Quick Safari through the Reconfiguration Jungle,” in Proc. of the 38th Design Automation Conference, Las Vegas, 2001, pp. 127–177.

[2]

Kephart J.O. and Chess D.M. The Vision of Autonomic Computing Computer 2003 36 41-52

[3]

IBM Autonomic Computing Initiative, (http://www.research.ibm.com/autonomic/).

[4]

Müller-Schloer C., von der Malsburg C., and Würtz R. P. Organic Computing Inform.-Spektrum 2004 27 332-336

[5]

The Organic Computing Page, (http://www.organic-computing.org).

[6]

SPP1148 Reconfigurable Computing Priority Program, (http://www12.informatik.uni-erlangen.de/spprr/).

[7]

A. Ahmadinia, C. Bobda, S. Fekete, J. Teich, and J. van der Veen, “Optimal Routing-conscious Dynamic Placement for Reconfigurable Devices,” in Proc. of International Conference on Field-Programmable Logic and Applications. Lecture Notes in Computer Science (LNCS), vol. 3203, Antwerp, Belgium, Springer, 2004, pp. 847–851.

[8]

Bazargan K., Kastner R., and Sarrafzadeh M. Fast Template Placement for Reconfigurable Computing Systems IEEE Des. Test Comput. 2000 17 68-83

[9]

M. Majer, J. Teich, and C. Bobda, “ESM – the Erlangen Slot Machine,” (http://www.r-space.de).

[10]

C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth, J. Teich, S. P. Fekete, and J. van der Veen, “The Erlangen Slot Machine: A Highly Flexible FPGA-based Reconfigurable Platform,” in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, 2005, pp. 319-320.

[11]

C. Bobda, A. Ahmadinia, M. Majer, J. Ding, and J. Teich, “Modular Video Streaming on a Reconfigurable Platform,” in Proc. of the IFIP International Conference on Very Large Scale Integration, Perth, Australia, 2005, pp. 103–108.

[12]

C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth, and J. Teich, “Increasing the Flexibility in FPGA-based Reconfigurable Platforms: The Erlangen Slot Machine,” in Proc. IEEE Conference on Field-Programmable Technology, Singapore, Singapore, 2005, pp. 37–42.

[13]

Y. Krasteva, A. Jimeno, E. Torre, and T. Riesgo, “Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs,” in Proc. of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, 2005, pp. 77–83.

[14]

V. Baumgarte, F. May, A. Nückel, M. Vorbach, and M. Weinhardt, “PACT XPP – a Self-reconfigurable Data Processing Architecture,” in ERSA, Las Vegas, Nevada, 2001, pp. 167–184.

[15]

Silicon Hive, (http://www.siliconhive.com).

[16]

PicoChip, (http://www.picochip.com).

[17]

Elixent Ltd., (http://www.elixent.com).

[18]

NEC DRP Project, ( http://www.necel.com/en/techhighlights/drp/).

[19]

Xilinx, Inc., (http://www.xilinx.com).

[20]

Celoxica Ltd., RC2000 Development Board, 2004.

[21]

Xess Corp., (http://www.xess.com).

[22]

Nallatech, Inc., (http://www.nallatech.com).

[23]

Alpha Data Ltd., ADM-XRC-II Xilinx Virtex-II PMC, 2002.

[24]

M. Platzner and L. Thiele, XFORCES – executives for Reconfigurable Embedded Systems, (http://www.ee.ethz.ch/~platzner).

[25]

C. Steiger, H. Walder, M. Platzner, and L. Thiele, “Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices,” in Proc. of the 24th International Real-Time Systems Symposium, Cancun, Mexico, 2003, pp. 224–235.

[26]

H. Kalte, M. Porrmann, and U. Rückert, “A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs,” in Proc. IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, 2002.

[27]

C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen, “DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices,” in Proc. of the International Conference on Field-Programmable Logic and Applications, Tampere, Finland, 2005, pp. 153–158.

[28]

P. Lysaght, B. Blodge, J. Mason, J. Young, and B. Bridgeford, “Enhanced Architectures, Design Methodologies and Cad Tools for Dynamic Reconfiguration of Xilinx FPGAs,” in Proc. of 16th International Conference on Field Programmable Logic and Applications (FPL06), Madrid, Spain, 2006.

[29]

A. Ahmadinia, J. Ding, C. Bobda, and J. Teich, “Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC),” Technical Report 02-2004, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, 2004.

[30]

S. Fekete, J. van der Veen, M. Majer, and J. Teich, “Minimizing Communication Cost for Reconfigurable Slot Modules,” in Proceedings of 16th International Conference on Field Programmable Logic and Applications (FPL06), Madrid, Spain, 2006.

[31]

H. A. ElGindy, A. K. Somani, H. Schröder, H. Schmeck, and A. Spray, “RMB – a Reconfigurable Multiple Bus Network,” in Proc. of the Second International Symposium on High-Performance Computer Architecture (HPCA-2), San Jose, California, 1996, pp. 108–117.

[32]

R. Vaidyanathan and J. L. Trahan, Dynamic Reconfiguration: Architectures and Algorithms, IEEE Computer Society, 2003.

[33]

A. Ahmadinia, C. Bobda, J. Ding, M. Majer, J. Teich, S. Fekete, and J. van der Veen, “A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices,” in Proc. of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, 2005, pp. 84–90.

[34]

R. Gonzalez and R. Woods, Digital Image Processing, Prentice Hall, 2002.

Cited By

Xiao YPark DNiu ZHota ADehon A(2023)ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA CompilationACM Transactions on Reconfigurable Technology and Systems10.1145/361783717:2(1-28)Online publication date: 14-Sep-2023
https://dl.acm.org/doi/10.1145/3617837
Xiao YMicallef EButt AHofmann MAlston MGoldsmith MMerczynski-Hait ADeHon AFalsafi BFerdman MLu SWenisch T(2022)PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software developmentProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507740(933-945)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507740
Vipin KFahmy S(2018)FPGA Dynamic and Partial ReconfigurationACM Computing Surveys10.1145/319382751:4(1-39)Online publication date: 25-Jul-2018
https://dl.acm.org/doi/10.1145/3193827
Show More Cited By

Index Terms

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
1. Computer systems organization
  1. Architectures
2. Software and its engineering
  1. Software organization and properties

Index terms have been assigned to the content through auto-classification.

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Information & Contributors

Information

Published In

cover image Journal of VLSI Signal Processing Systems

Journal of VLSI Signal Processing Systems Volume 47, Issue 1

Apr 2007

89 pages

ISSN:0922-5773

Issue’s Table of Contents

© Springer Science+Business Media, LLC 2007.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 April 2007

Accepted: 15 November 2006

Revision received: 13 November 2006

Received: 01 February 2006

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Cited By

Xiao YPark DNiu ZHota ADehon A(2023)ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA CompilationACM Transactions on Reconfigurable Technology and Systems10.1145/361783717:2(1-28)Online publication date: 14-Sep-2023
https://dl.acm.org/doi/10.1145/3617837
Xiao YMicallef EButt AHofmann MAlston MGoldsmith MMerczynski-Hait ADeHon AFalsafi BFerdman MLu SWenisch T(2022)PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software developmentProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507740(933-945)Online publication date: 28-Feb-2022
https://dl.acm.org/doi/10.1145/3503222.3507740
Vipin KFahmy S(2018)FPGA Dynamic and Partial ReconfigurationACM Computing Surveys10.1145/319382751:4(1-39)Online publication date: 25-Jul-2018
https://dl.acm.org/doi/10.1145/3193827
An XRutten EDiguet JGamatié A(2016)Model-Based Design of Correct Controllers for Dynamically Reconfigurable ArchitecturesACM Transactions on Embedded Computing Systems10.1145/287305615:3(1-27)Online publication date: 23-May-2016
https://dl.acm.org/doi/10.1145/2873056
Dumitriu VKirischian L(2016)SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.241775224:2(799-802)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2417752
Beckhoff CKoch DTorresen J(2014)Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/26175977:2(1-23)Online publication date: 4-Jul-2014
https://dl.acm.org/doi/10.1145/2617597
Neely CBrebner GShang W(2013)ReShapeACM Transactions on Reconfigurable Technology and Systems10.1145/2457443.24574486:1(1-23)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1145/2457443.2457448
Syed RHa YVeeravalli B(2012)A low overhead abstract architecture for FPGA resource managementACM SIGARCH Computer Architecture News10.1145/2460216.246022240:5(28-33)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2460216.2460222
Fons FFons MCantó ELópez M(2012)Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded ApplicationsJournal of Signal Processing Systems10.1007/s11265-011-0607-966:2(191-221)Online publication date: 1-Feb-2012
https://dl.acm.org/doi/10.1007/s11265-011-0607-9
Philippe JTain BGamrat C(2010)A self-reconfigurable FPGA-based platform for prototyping future pervasive systemsProceedings of the 9th international conference on Evolvable systems: from biology to hardware10.5555/1885332.1885362(262-273)Online publication date: 6-Sep-2010
https://dl.acm.org/doi/10.5555/1885332.1885362
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