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Co-optimization of buffer layer and FTL in high-performance flash-based storage systems

Authors:

Seungryoul MaengAuthors Info & Claims

Design Automation for Embedded Systems, Volume 14, Issue 4

Pages 415 - 443

https://doi.org/10.1007/s10617-010-9066-y

Published: 01 December 2010 Publication History

Abstract

NAND flash-based storage devices have rapidly improved their position in the secondary storage market ranging from mobile embedded systems to personal computer and enterprise storage systems. Recently, the most important issue of NAND flash-based storage systems is the performance of random writes as well as sequential writes, which strongly depends on their two main software layers: a Buffer Management Layer (BML) and a Flash Translation Layer (FTL). The primary goal of our study is to highly improve the overall performance of NAND flash-based storage systems by exploiting the cooperation between those two layers. In this paper, we propose an FTL-aware BML policy called Selective Block Padding and a BML-based FTL algorithm called Optimized Switch Merge, which overcome the limitations of existing approaches on performance enhancement. When using both the proposed techniques, evaluation results show that the throughput is significantly increased over that of previous studies.

References

[1]

1 G × 8 Bit/2 G × 8 Bit/4 G × 8 Bit NAND flash memory (K9WAG08U1M) data sheets, Samsung Electronics, Nov 2005

[2]

2 G × 8 Bit NAND flash memory (K9GAG08UXM) data sheets, Samsung Electronics, Dec 2006

[3]

Baek S, Choi J, Ahn S, Lee D, Noh SH (2009) Design and implementation of a uniformity-improving page allocation scheme for flash-based storage systems. Des Autom Embed Syst 13(1---2):5---25

[4]

Lim S-H, Park KH (2006) An efficient NAND flash file system for flash memory storage. IEEE Trans Comput 55(7):906---912

Digital Library

[5]

Lee C, Baek SH, Park KH (2008) A hybrid flash file system based on nor and nand flash memories for embedded devices. IEEE Trans Comput 57(7):1002---1008

Digital Library

[6]

Caulfield AM, Grupp LM, Swanson S (2009) Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications. In: Proceedings of the 14th international conference on architectural support for programming languages and operating systems (ASPLOS'09), Washington, DC, USA, Mar 2009, pp 217---228

[7]

Chen F, Koufaty DA, Zhang X (2009) Understanding intrinsic characteristics and system implications of flash memory based solid state drives. In: ACM SIGMETRICS/performance, Seattle, WA, USA, Jun 2009, pp 181---192

[8]

Prabhakaran V, Rodeheffer TL, Zhou L (2008) Transactional flash. In: Proceedings of the 8th USENIX symposium on operating systems design and implementation (OSDI'08), San Diego, CA, USA, Dec 2008, pp 147---160

[9]

Kang J-U, Kim J-S, Park C, Park H, Lee J (2007) A multi-channel architecture for high-performance NAND flash-based storage system. J Syst Archit 53(9):644---658

Digital Library

[10]

Agrawal N, Prabhakaran V, Wobber T, Davis JD, Manasse M, Panigrahy R (2008) Design tradeoffs for SSD performance. In: Proceedings of USENIX annual technical conference (USENIX'08), Boston, MA, USA, Jun 2008, pp 57---70

[11]

Kim H, Ahn S (2008) A buffer management scheme for improving random writes in flash storage. In: Proceedings of the 6th USENIX conference on file and storage technologies (FAST'08), San Jose, CA, USA, Feb 2008, pp 239---252

[12]

Park S-Y, Jung D, Kang J-U, Kim J-S, Lee J (2006) CFLRU: a replacement algorithm for flash memory. In: Proceedings of the international conference on compilers, architecture and synthesis for embedded systems (CASES'06) held in conjunction with ESWEEK'06, Seoul, Republic of Korea, Oct 2006, pp 234---241

[13]

Jo H, Kang J-U, Park S-Y, Kim J-S, Lee J (2006) FAB: flash-aware buffer management policy for portable media players. IEEE Trans Consum Electron 52(2):485---493

Digital Library

[14]

Seo D, Shin D (2008) Recently-evicted-first buffer replacement policy for flash storage devices. IEEE Trans Consum Electron 54(3):1228---1235

Digital Library

[15]

Lee S, Shin D, Kim J (2008) Buffer-aware garbage collection for NAND flash memory-based storage systems. In: Proceedings of the international workshop on software support for portable storage (IWSSPS'08) held in conjunction with ESWEEK'08, Atlanta, GA, USA, Oct 2008, pp 27---32

[16]

Ding X, Jiang S, Chen F (2007) A buffer cache management scheme exploiting both temporal and spatial localities. ACM Trans Storage 3(2):5

Digital Library

[17]

Chiang M-L, Lee PCH, Chang R-C (1999) Using data clustering to improve cleaning performance for flash memory. Softw Pract Exp 29(3):267---290

Digital Library

[18]

Gupta A, Kim Y, Urgaonkar B (2009) DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In: Proceeding of the 14th international conference on architectural support for programming languages and operating systems (ASPLOS), Washington, DC, USA, Mar 2009, pp 229---240

[19]

Kim J, Kim JM, Noh SH, Min SL, Cho Y (2002) A space-efficient flash translation layer for compactflash systems. IEEE Trans Consum Electron 48(2):366---375

Digital Library

[20]

Lee S-W, Park D-J, Chung T-S, Lee D-H, Park S, Song H-J (2007) A log buffer-based flash translation layer using fully-associative sector translation. ACM Trans Embed Comput Syst 6(3):18

Digital Library

[21]

Kang J-U, Jo H, Kim J-S, Lee J (2006) A superblock-based flash translation layer for NAND flash memory. In: Proceedings of the 6th ACM international conference on embedded software (EMSOFT'06), Seoul, Republic of Korea, Oct 2006, pp 161---170

[22]

Lee Y-G, Jung D, Kang D, Kim J-S (2008) μ-FTL: a memory-efficient flash translation layer supporting multiple mapping granularities. In: Proceedings of the 8th ACM international conference on embedded software (EMSOFT'08), Atlanta, GA, USA, Oct 2008, pp 21---30

Digital Library

[23]

Park C, Cheon W, Kang J, Roh K, Cho W (2008) A reconfigurable FTL (Flash Translation Layer) architecture for NAND flash-based applications. ACM Trans Embed Comput Syst 7(4):38

[24]

Choi HJ, Lim S-H, Park KH (2009) JFTL: a flash translation layer based on a journal remapping for flash memory. ACM Trans Storage 4(4):14

Digital Library

[25]

Lee J, Kim S, Kwon H, Hyun C, Ahn S, Choi J, Lee D, Noh SH (2007) Block recycling schemes and their cost-based optimization in NAND flash memory based storage system. In: Proceedings of the 7th ACM international conference on embedded software (EMSOFT'07), Salzburg, Austria, Sep 2007, pp 174---182

[26]

Kang S, Park S, Jung H, Shim H, Cha J (2009) Performance trade-offs using NVRAM write buffer for flash memory-based storage devices. IEEE Trans Comput 58(6):744---758

Digital Library

[27]

Lee BC, Ipek E, Mutlu O, Burger D (2009) Architecting phase change memory as a scalable DRAM alternative. In: Proceedings of the 36th international symposium on computer architecture (ISCA), Austin, TX, USA, Jun 2009, pp 1---12

[28]

Yoon JH, Nam EH, Seong YJ, Kim H, Kim BS, Min SL, Cho Y (2008) Chameleon: a high performance flash/FRAM hybrid solid state disk architecture. IEEE Comput Archit Lett 7(1):17---20

Digital Library

[29]

Sun K, Baek S, Choi J, Lee D, Noh SH, Min SL (2008) LTFTL: lightweight time-shift flash translation layer for flash memory based embedded storage. In: Proceedings of the 8th ACM international conference on embedded software (EMSOFT'08), Atlanta, Georgia, USA, Oct 2008, pp 51---58

[30]

Hsieh J-W, Tsai Y-L, Kuo T-W, Lee T-L (2008) Configurable flash-memory management: performance versus overheads. IEEE Trans Comput 57(11):1571---1583

Digital Library

[31]

Llanos DR TPCC-uva: an open-source implementation of the TPC-C benchmark, installation and user guide, version 1.2. http://www.infor.uva.es/~diego/tpcc-uva.html (2006)

[32]

Narayanan D, Donnelly A, Rowstron A (2008) Write off-loading: practical power management for enterprise storage. In: Proceedings of the 6th USENIX Conference on File and Storage Technologies (FAST'08), San Jose, CA, USA, Feb 2008, pp 253---267

Cited By

Lim SJeong Y(2014)Journaling deduplication with invalidation scheme for flash storage-based smart systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2014.04.00260:8(684-692)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.sysarc.2014.04.002
Lee YBarolli LLim S(2013)Mapping granularity and performance tradeoffs for solid state driveThe Journal of Supercomputing10.1007/s11227-012-0798-265:2(507-523)Online publication date: 1-Aug-2013
https://dl.acm.org/doi/10.1007/s11227-012-0798-2
Paik JChung TCho E(2013)Loop transformations for flash memoryDesign Automation for Embedded Systems10.1007/s10617-014-9144-717:3-4(627-667)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1007/s10617-014-9144-7

Co-optimization of buffer layer and FTL in high-performance flash-based storage systems
1. General and reference
  1. Cross-computing tools and techniques
2. Social and professional topics
  1. Professional topics
    1. Computing profession

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Information

Published In

cover image Design Automation for Embedded Systems

Design Automation for Embedded Systems Volume 14, Issue 4

December 2010

115 pages

ISSN:0929-5585

Issue’s Table of Contents

Copyright © Copyright © 2011 Springer Science+Business Media, LLC.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 December 2010

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Cited By

Lim SJeong Y(2014)Journaling deduplication with invalidation scheme for flash storage-based smart systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2014.04.00260:8(684-692)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.sysarc.2014.04.002
Lee YBarolli LLim S(2013)Mapping granularity and performance tradeoffs for solid state driveThe Journal of Supercomputing10.1007/s11227-012-0798-265:2(507-523)Online publication date: 1-Aug-2013
https://dl.acm.org/doi/10.1007/s11227-012-0798-2
Paik JChung TCho E(2013)Loop transformations for flash memoryDesign Automation for Embedded Systems10.1007/s10617-014-9144-717:3-4(627-667)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1007/s10617-014-9144-7

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