Fast Sobel Edge Detection for IoT Edge Devices

The emerging IoT edge applications demand fast and energy-efficient hardware requirements for data processing. Conventional computing architectures are quite inefficient for meeting these stringent requirements as they incur high performance and energy costs. We proposed a novel CMOS VLSI bit-sliced near-memory computing architecture for rapid Sobel edge detection for IoT edge devices to address this issue. The proposed architecture is compact, modular, scalable, and capable of processing a single image in a constant amount of time, irrespective of image resolution. The gate-level implementation of the block processing element is performed using the Synopsys Design Compiler tool in 32 nm CMOS technology node using SAED 32 nm PDK. The processing of a single block frame (3 × 3 pixel block array) requires 22 logic gates with a total area of 111 nm${}^2$, a worst-case delay of 1.5 fs, and the average power dissipation of 2.27 $\mathrm{\mu }$W at a supply voltage of 1.05 V. We exhaustively tested our model varying the image resolutions (28 × 28, 128 × 128, 256 × 256, and 512 × 512 pixels images). We extended this work by designing gate-level architectures for Roberts cross and Prewitt detection kernels. And, we also designed the layout of one block frame and Sobel edge detection block array (28 × 28 pixels) to verify our model. The proposed architecture can be easily extended to other block-based algorithms. A preliminary version of this work appeared in iSES 2020 [1].