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Article

Modelling SAMIPS: A Synthesisable Asynchronous MIPS Processor

Published: 18 April 2004 Publication History

Abstract

The last fifteen years have witnessed a resurgence ofinterest in asynchronous digital design techniques as theypromise to liberate VLSI systems from clock skew problems,offer the potential for low power and high performanceand encourage a modular design philosophy whichmakes incremental technological migration a much easiertask. This activity has revealed a need for modelling andsimulation techniques suitable for the asynchronous designstyle. The concurrent process algebra Communication SequentialProcesses (CSP) is increasingly advocated as particularlysuitable for this purpose. This paper discusses themodelling of SAMIPS, a synthesisable asynchronous MIPSprocessor core, in Balsa, a CSP-based, asynchronous hardwaredescription language and synthesis tool.

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Cited By

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  • (2006)A Framework for Distributed Simulation of Asynchronous Handshake CircuitsProceedings of the 39th annual Symposium on Simulation10.1109/ANSS.2006.5(214-222)Online publication date: 2-Apr-2006
  • (2006)Sim-asyncProceedings of the 12th international conference on Parallel Processing10.1007/11823285_51(495-505)Online publication date: 28-Aug-2006

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cover image ACM Conferences
ANSS '04: Proceedings of the 37th annual symposium on Simulation
April 2004
275 pages
ISBN:076952110X

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IEEE Computer Society

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Published: 18 April 2004

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View all
  • (2006)A Framework for Distributed Simulation of Asynchronous Handshake CircuitsProceedings of the 39th annual Symposium on Simulation10.1109/ANSS.2006.5(214-222)Online publication date: 2-Apr-2006
  • (2006)Sim-asyncProceedings of the 12th international conference on Parallel Processing10.1007/11823285_51(495-505)Online publication date: 28-Aug-2006

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